AD6679135 MHz BW IF Diversity Receiver | RF Misc ICs and Modules | 3 | Active | The AD6679 is a 135 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit, 500 MSPS analog-to-digital converters (ADCs) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6679 is optimized for wide input bandwidth, high sampling rates, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.ApplicationsDiversity multiband, multimode digital receivers3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-ADOCSIS 3.0 CMTS upstream receive pathsHFC digital reverse path receivers |
AD6684135 MHz Quad IF Receiver | RF Misc ICs and Modules | 2 | Active | The AD6684 is a 135 MHz bandwidth, quad intermediate frequency (IF) receiver. It consists of four 14-bit, 500 MSPS ADCs and various digital processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support communications applications. The analog full power bandwidth of the device is 1.4 GHz.The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD6684 is optimized for wide input bandwidth, excellent linearity, and low power in a small package.The analog inputs and clock signal input are differential. Each pair of ADC data outputs are internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters.Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6684 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution.Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution.With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications andsupports tunable real IF sampling, and zero IF or complex IF receive architectures.Operation of the AD6684 in the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles (the default mode is NSR at startup).In addition to the DDC blocks, the AD6684 has several functions that simplify the AGC function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure each pair of IF receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins.The AD6684 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI.The AD6684 is available in a Pb-free, 72-lead LFCSP and is specified over the −40°C to +105°C junction temperature range.Product HighlightsLow power consumption per channel.JESD204B lane rate support up to 15 Gbps.Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz.Buffered inputs ease filter design and implementation.Four integrated wideband decimation filters and NCO blocks supporting multiband receivers.Programmable fast overrange detection.On-chip temperature diode for system thermal management.ApplicationsCommunicationsDiversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-AHFC digital reverse path receiversDigital predistortion observation pathsGeneral-purpose software radios |
AD6688RF Diversity and 1.2GHz BW Observation Receiver | RF and Wireless | 2 | Active | The AD6688 is a 1.2 GHz bandwidth, mixed-signal, direct radio frequency (RF) sampling receiver. It consists of two 14-bit, 3.0 GSPS analog-to-digital converters (ADCs) and various digital signal processing blocks consisting of four wideband digital downconverters (DDCs). The AD6688 has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The 3 dB bandwidth of the ADC input is greater than 9 GHz. The AD6688 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit numerically controlled oscillator (NCO) and up to four half-band decimation filters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables selection of up to three bands. Operation of the AD6688 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD6688 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Besides the fast detect outputs, the AD6688 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, six-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD6688 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).The AD6688 is available in a Pb-free, 196-ball BGA specified over the −40°C to +85°C ambient temperature range.Product HighlightsWide full power bandwidth supports IF sampling of signals up to 9GHz (-3dB point).Four Integrated wide-band decimation filter and NCO blocks supporting multi-band receivers.Fast NCO switching enabled through GPIO pins.Flexible SPI interface controls various product features and functions to meet specific system requirements.Programmable fast overrange detection and signal monitoring.On-chip temperature dioide for system thermal management.12mm x 12mm 196-Lead BGAApplicationsDiversity multiband, multimode digital receivers3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-ADOCSIS 3.0 CMTS upstream receive pathsHFC digital reverse path receivers |
| Integrated Circuits (ICs) | 11 | Active | |
| Data Acquisition | 8 | Active | |
AD6738-bit Successive Approximation, ADC | Integrated Circuits (ICs) | 4 | Active | The AD673 is a complete 8-bit successive approximation analog-to-digital converter consisting of a DAC, voltage reference, clock, comparator, successive approximation register (SAR) and 3-state output buffers-all fabricated on a single chip. No external components are required to perform a full ac-curacy 8-bit conversion in 20 µs.The AD673 incorporates advanced integrated circuit design and processing technologies. The successive approximation function is implemented with I2L (integrated injection logic). Laser trimming of the high stability SiCr thin-film resistor ladder network insures high accuracy, which is maintained with a temperature compensated sub-surface Zener reference.Operating on supplies of +5 V and −12 V to −15 V, the AD673 will accept analog inputs of 0 V to +10 V or −5 V to +5 V. The trailing edge of a positive pulse on the CONVERT line initiates the 20 µs conversion cycle.DATA READYindicates completion of the conversion.The AD673 is available in two versions. The AD673J as specified over the 0°C to +70°C temperature range and the AD673S guarantees ±1/2 LSB relative accuracy and no missing codes from −55°C to +125°C.Two package configurations are offered. All versions are also offered in a 20-pin hermetically sealed ceramic DIP. The AD673J is also available in a 20-pin plastic DIP. |
| Data Acquisition | 11 | Active | |
| Development Boards, Kits, Programmers | 12 | Active | |
| Development Boards, Kits, Programmers | 16 | Active | |
AD67812-Bit 200 kSPS Complete Sampling ADC | Integrated Circuits (ICs) | 10 | Active | The AD678 is a complete, multipurpose 12-bit monolithic analog-to-digital converter, consisting of a sample-hold amplifier (SHA), a microprocessor compatible bus interface, a voltage reference and clock generation circuitry.The AD678 is specified for ac (or "dynamic") parameters such as S/N+D ratio, THD and IMD which are important in signal processing applications. In addition, the AD678K, B and T grades are fully specified for dc parameters which are important in measurement applications.The AD678 offers a choice of digital interface formats; the 12 data bits can be accessed by a 16-bit bus in a single read operation or by an 8-bit bus in two read operations (8+4), with right or left justification. Data format is straight binary for unipolar mode and twos complement binary for bipolar mode. The input has a full-scale range of 10 V with a full power bandwidth of 1 MHz and a full linear bandwidth of 500 kHz. High input impedance (10 MΩ) allows direct connection to unbuffered sources without signal degradation.This product is fabricated on Analog Devices' BiMOS process, combining low power CMOS logic with high precision, low noise bipolar circuits; laser-trimmed thin-film resistors provide high accuracy. The converter utilizes a recursive subranging algorithm which includes error correction and flash converter circuitry to achieve high speed and resolution.The AD678 operates from +5 V and ±12 V supplies and dissipates 560 mW (typ). The AD678 is available in 28-pin plastic DIP, ceramic DIP, and 44 J-leaded ceramic surface mount packages.Screening to MIL-STD-883C Class B is also available.PRODUCT HIGHLIGHTSCOMPLETE INTEGRATION: The AD678 minimizes external component requirements by combining a high speed sample-hold amplifier (SHA), ADC, 5 V reference, clock and digital interface on a single chip. This provides a fully specified sampling A/D function unattainable with discrete designs.SPECIFICATIONS: The AD678K, B and T grades provide fully specified and tested ac and dc parameters. The AD678J, A and S grades are specified and tested for ac parameters; dc accuracy specifications are shown as typicals. DC specifications (such as INL, gain and offset) are important in control and measurement applications. AC specifications (such as S/N+D ratio, THD and IMD) are of value in signal processing applications.EASE OF USE: The pinout is designed for easy board lay-out, and the choice of single or two read cycle output provides compatibility with 16- or 8-bit buses. Factory trimming eliminates the need for calibration modes or external trimming to achieve rated performance.RELIABILITY: The AD678 utilizes Analog Devices’ monolithic BiMOS technology. This ensures long-term reliability compared to multichip and hybrid designs.UPGRADE PATH: The AD678 provides the same pinout as the 14-bit, 128 kSPS AD679 ADC.The AD678 is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD678/883B data sheet for detailed specifications. |
