Analog Devices Inc./Maxim Integrated

The AD6655 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6655 is designed to support communications applications where low cost, small size, and versatility are desired.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver, simplifying layout and reducing interconnection parasitics. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO)), a half-band decimating filter, a fixed FIR filter, and an fADC/8 fixed-frequency NCO.In addition to the receiver DDC, the AD6655 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with short latency.In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition.The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.After digital processing, data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or as 1.8 V LVDS. The CMOS data can also be output in an interleaved configuration at a double data rate using only Port A.The AD6655 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.The AD6655 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.Product HighlightsIntegrated dual, 14-bit, 150 MSPS ADC.Integrated wideband decimation filter and 32-bit complex NCO.Fast overrange detect and signal monitor with serial output.Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz.Flexible output modes, including independent CMOS, interleaved CMOS, IQ mode CMOS, and interleaved LVDS.SYNC input allows synchronization of multiple devices.3-bit SPI port for register programming and register readback.ApplicationsCommunicationsDiversity radio systemsMultimode digital receivers (3G)TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTEI/Q demodulation systemsSmart antenna systemsGeneral-purpose software radiosBroadband data applications

The AD6657 is an 11-bit, 200 MSPS, quad-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.The device consists of four high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched-capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the external MODE pin or the SPI.With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6657 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6657 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.With the NSR block disabled, the ADC data is provided directly to the output with a resolution of 11 bits. The AD6657 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6657 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are desired.After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are set at 1.8 V LVDS and support ANSI-644 levels.The AD6657 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board-level system testing.The AD6657 is available in a Pb-free/RoHS compliant, 144-ball, 10 mm × 10 mm chip scale package ball grid array (CSP_BGA) and is specified over the industrial temperature range of −40°C to +85°C.APPLICATIONSCommunicationsDiversity radio and smart antenna (MIMO) systemsMultimode digital receivers (3G)WCDMA, LTE, CDMA2000WiMAX, TD-SCDMAI/Q demodulation systemsGeneral-purpose software radiosPRODUCT HIGHLIGHTSFour ADCs are contained in a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package.Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS.LVDS digital output interface configured for low cost FPGA families.230 mW per ADC core power consumption.Operation from a single 1.8 V supply.Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode.On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.

The AD6657A is an 11-bit, 200 MSPS, quad channel intermediate frequency (IF) receiver specifically designed to support multiple antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.The device consists of four high performance ADCs and NSR digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the external MODE pin or the SPI.With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6657A supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22%, 33%, or 36% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6657A can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode, up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode, or up to 70.0 dBFS SNR for a 65 MHz bandwidth in the 36% mode.With the NSR block disabled, the ADC data is provided directly to the output with a resolution of 11 bits. The AD6657A can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6657A to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are used.After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are set at 1.8 V LVDS and support ANSI-644 levels. The AD6657A receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board level system testing.The AD6657A is available in a Pb-free, RoHS-compliant, 144 ball, 10 mm × 10 mm chip scale package ball grid array (CSP_BGA) that is specified over the industrial temperature range of −40°C to +85°C.APPLICATIONSCommunicationsDiversity radio and smart antenna (MIMO) systemsMultimode digital receivers (3G)WCDMA, LTE, CDMA2000WiMAX, TD-SCDMAI/Q demodulation systemsGeneral-purpose software radiosPRODUCT HIGHLIGHTSFour analog-to-digital converters (ADCs) are contained in a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package.Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 65 MHz at 185 MSPS.LVDS digital output interface configured for low cost FPGA families.230 mW per ADC core power consumption. 5. Operation from a single 1.8 V supply.Standard SPI that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode.On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.

The AD6673 is an 11-bit, 250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6673 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution.The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 250 MSPS, the AD6673 can achieve up to 76.3 dBFS SNR for a 55 MHz bandwidth in the 22% mode and up to 73.5 dBFS SNR for a 82 MHz bandwidth in the 33% mode.When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6673 can achieve up to 65.9 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6673 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required.By default the ADC output data is routed directly to the two external JESD204B serial output lanes. These outputs are at current mode logic (CML) voltage levels. Two modes are supported such that output coded data is either sent through one lane or two (L = 1; F = 4 or L = 2; F = 2). Single lane operation supports converter rates up to 125 MSPS. Synchronization input controls (SYNCINB± and SYSREF±) are provided.PRODUCT HIGHLIGHTSThe configurable JESD204B output block with an integrated phase-locked loop (PLL) to support up to 5 Gbps per lane with up to two lanes.IF receiver includes two, 11-bit, 250 MSPS ADCs with programmable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of 22% or 33% of the sample rate.Support for an optional RF clock input to ease system board design.Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz.An on-chip integer, 1-to-8 input clock divider and SYNC input allows synchronization of multiple devices.Operation from a single 1.8 V power supply.Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, overrange fast detection, and serial output configuration.APPLICATIONSCommunicationsDiversity radio and smart antenna (MIMO) systemsMultimode digital receivers (3G)TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTEI/Q demodulation systemsGeneral-purpose software radios

The AD6676 is a highly integrated IF subsystem that can digitize radio frequency (RF) bands up to 160 MHz in width centered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, the AD6676 relies on a tunable band-pass Σ-Δ ADC with a high oversampling ratio to eliminate the need for band specific IF SAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadrature digital downconversion followed by selectable decimation filters reduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interface supporting line rates of up to 5.333 Gbps.ApplicationsWideband cellular infrastructure equipment and repeatersPoint-to-point microwave equipmentInstrumentationSpectrum and communication analyzersSoftware defined radio