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Integrated Circuits (ICs)

SN74HC164NE4

Unknown
Texas Instruments

8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

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PDIP (N)
Integrated Circuits (ICs)

SN74HC164NE4

Unknown
Texas Instruments

8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74HC164NE4
FunctionSerial to Parallel
Logic TypeShift Register
Mounting TypeThrough Hole
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypePush-Pull
Package / Case14-DIP
Package / Case [x]0.3 "
Package / Case [y]7.62 mm
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 3125$ 0.13
Texas InstrumentsTUBE 1$ 0.62
100$ 0.42
250$ 0.33
1000$ 0.22

Description

General part information

SN74HC164A Series

These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.