SN74HC164PW
Obsolete8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
Deep-Dive with AI
Search across all available documentation for this part.
SN74HC164PW
Obsolete8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74HC164PW |
|---|---|
| Function | Serial to Parallel |
| Logic Type | Shift Register |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Push-Pull |
| Package / Case | 14-TSSOP |
| Package / Case [custom] | 0.173 " |
| Package / Case [custom] | 4.4 mm |
| Supplier Device Package | 14-TSSOP |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 1.10 | |
| 10 | $ 0.99 | |||
| 90 | $ 0.77 | |||
| 270 | $ 0.72 | |||
| 540 | $ 0.64 | |||
| Texas Instruments | TUBE | 1 | $ 0.82 | |
| 100 | $ 0.63 | |||
| 250 | $ 0.46 | |||
| 1000 | $ 0.33 | |||
Description
General part information
SN74HC164A Series
These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
Documents
Technical documentation and resources
