SN74HC164A Series

High Speed CMOS Logic 8-Bit Serial-In/Parallel-Out Shift Register

Catalog

High Speed CMOS Logic 8-Bit Serial-In/Parallel-Out Shift Register

Part	Number of Bits per Element	Operating Temperature [Min]	Operating Temperature [Max]	Logic Type	Number of Elements	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Package / Case [x]	Package / Case [y]	Package / Case	Output Type	Function	Supplier Device Package	Package / Case [custom]	Package / Case [custom]
Texas Instruments CD74HC164M96G4	8	-55 °C	125 °C	Shift Register	1	2 V	6 V	Surface Mount	0.154 in	3.9 mm	14-SOIC	Push-Pull	Serial to Parallel
Texas Instruments SN74HC164NE4	8	-40 °C	125 °C	Shift Register	1	2 V	6 V	Through Hole	0.3 "	7.62 mm	14-DIP	Push-Pull	Serial to Parallel
Texas Instruments SN74HC164N	8	-40 °C	125 °C	Shift Register	1	2 V	6 V	Through Hole	0.3 "	7.62 mm	14-DIP	Push-Pull	Serial to Parallel
Texas Instruments SN74HC164DRG3	8	-40 °C	125 °C	Shift Register	1	2 V	6 V	Surface Mount	0.154 in	3.9 mm	14-SOIC	Push-Pull	Serial to Parallel
Texas Instruments SN74HC164PW	8	-40 °C	125 °C	Shift Register	1	2 V	6 V	Surface Mount			14-TSSOP	Push-Pull	Serial to Parallel	14-TSSOP	0.173 "	4.4 mm
Texas Instruments CD74HC164MT	8	-55 °C	125 °C	Shift Register	1	2 V	6 V	Surface Mount	0.154 in	3.9 mm	14-SOIC	Push-Pull	Serial to Parallel
Texas Instruments SN74HC164NSR	8	-40 °C	125 °C	Shift Register	1	2 V	6 V	Surface Mount	0.209 "	5.3 mm	14-SOIC	Push-Pull	Serial to Parallel	14-SO
Texas Instruments CD74HC164ME4	8	-55 °C	125 °C	Shift Register	1	2 V	6 V	Surface Mount	0.154 in	3.9 mm	14-SOIC	Push-Pull	Serial to Parallel
Texas Instruments CD74HC164M	8	-55 °C	125 °C	Shift Register	1	2 V	6 V	Surface Mount	0.154 in	3.9 mm	14-SOIC	Push-Pull	Serial to Parallel
Texas Instruments SN74HC164ANSR	8	-40 °C	85 °C	Shift Register	1	2 V	6 V	Surface Mount	0.209 "	5.3 mm	14-SOIC	Push-Pull	Serial to Parallel	14-SO

Catalog

High Speed CMOS Logic 8-Bit Serial-In/Parallel-Out Shift Register

Key Features

• Buffered inputsAsynchronous resetTypical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°CFanout (overtemperature range)Standard Outputs: 10 LSTTL loadsBus driver outputs: 15 LSTTL loadsWide operating temp range: – 55°C to 125°CBalanced propagation delay and transition timesSignificant power reduction compared to LSTTL logic ICsHC types2V to 6V operationHigh noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5VHCT types4.5V to 5.5V operationDirect LSTTL input logic compatibility, VIL = 0.8V (Max), VIH = 2V (Min)CMOS input compatibility, II ≤ 1µA at VOL, VOHBuffered inputsAsynchronous resetTypical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°CFanout (overtemperature range)Standard Outputs: 10 LSTTL loadsBus driver outputs: 15 LSTTL loadsWide operating temp range: – 55°C to 125°CBalanced propagation delay and transition timesSignificant power reduction compared to LSTTL logic ICsHC types2V to 6V operationHigh noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5VHCT types4.5V to 5.5V operationDirect LSTTL input logic compatibility, VIL = 0.8V (Max), VIH = 2V (Min)CMOS input compatibility, II ≤ 1µA at VOL, VOH

Description

These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.