CD74HC164MT
ObsoleteHIGH SPEED CMOS LOGIC 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER
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CD74HC164MT
ObsoleteHIGH SPEED CMOS LOGIC 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HC164MT |
|---|---|
| Function | Serial to Parallel |
| Logic Type | Shift Register |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Push-Pull |
| Package / Case | 14-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 2.11 | |
| 10 | $ 1.35 | |||
| 25 | $ 1.15 | |||
| 100 | $ 0.92 | |||
| Digi-Reel® | 1 | $ 1.43 | ||
| 10 | $ 1.27 | |||
| 25 | $ 1.21 | |||
| 100 | $ 0.99 | |||
| Tape & Reel (TR) | 750 | $ 0.82 | ||
| 1250 | $ 0.65 | |||
| 2500 | $ 0.61 | |||
| 6250 | $ 0.57 | |||
| 12500 | $ 0.55 | |||
| Texas Instruments | SMALL T&R | 1 | $ 1.06 | |
| 100 | $ 0.81 | |||
| 250 | $ 0.60 | |||
| 1000 | $ 0.43 | |||
Description
General part information
SN74HC164A Series
These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
Documents
Technical documentation and resources
