CD74HC112NSR
ActiveHIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
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CD74HC112NSR
ActiveHIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HC112NSR |
|---|---|
| Clock Frequency | 60 MHz |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Output High, Low [custom] | 5.2 mA |
| Current - Quiescent (Iq) | 4 çA |
| Function | Reset, Set(Preset) |
| Input Capacitance | 10 pF |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Complementary |
| Package / Case | 0.209 " |
| Package / Case | 16-SOIC |
| Package / Case | 5.3 mm |
| Supplier Device Package | 16-SO |
| Trigger Type | Negative Edge |
| Type | JK Type |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.27 | |
| 10 | $ 0.79 | |||
| 25 | $ 0.67 | |||
| 100 | $ 0.53 | |||
| 250 | $ 0.46 | |||
| 500 | $ 0.41 | |||
| 1000 | $ 0.38 | |||
| Digi-Reel® | 1 | $ 1.27 | ||
| 10 | $ 0.79 | |||
| 25 | $ 0.67 | |||
| 100 | $ 0.53 | |||
| 250 | $ 0.46 | |||
| 500 | $ 0.41 | |||
| 1000 | $ 0.38 | |||
| Tape & Reel (TR) | 2000 | $ 0.32 | ||
| 4000 | $ 0.29 | |||
| 6000 | $ 0.28 | |||
| 10000 | $ 0.27 | |||
| 14000 | $ 0.26 | |||
| 20000 | $ 0.25 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.70 | |
| 100 | $ 0.48 | |||
| 250 | $ 0.37 | |||
| 1000 | $ 0.24 | |||
Description
General part information
CD74HC112 Series
The SNx4HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high.
The SNx4HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high.
Documents
Technical documentation and resources
