Integrated Circuits (ICs)

SN74HC112D

Obsolete

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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Search across all available documentation for this part.

DocumentsPower-Up Behavior of Clocked Devices (Rev. B)Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)+14

Integrated Circuits (ICs)

SN74HC112D

Obsolete

Texas Instruments

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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DocumentsPower-Up Behavior of Clocked Devices (Rev. B)Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)+14

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74HC112D

Clock Frequency	60 MHz
Current - Output High, Low [custom]	5.2 mA
Current - Output High, Low [custom]	5.2 mA
Current - Quiescent (Iq)	4 çA
Function	Reset, Set(Preset)
Input Capacitance	3 pF
Max Propagation Delay @ V, Max CL	21 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Complementary
Package / Case	16-SOIC
Package / Case [x]	0.154 in
Package / Case [y]	3.9 mm
Supplier Device Package	16-SOIC
Trigger Type	Negative Edge
Type	JK Type
Voltage - Supply [Max]	6 V
Voltage - Supply [Min]	2 V

CD74HC112 Series

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset

Part	Operating Temperature [Max]	Operating Temperature [Min]	Current - Quiescent (Iq)	Input Capacitance	Number of Elements	Mounting Type	Clock Frequency	Function	Type	Package / Case [x]	Package / Case	Package / Case [y]	Number of Bits per Element	Trigger Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Output Type	Operating Temperature [Max]	Operating Temperature [Min]	Max Propagation Delay @ V, Max CL	Package / Case	Package / Case
Texas Instruments CD74HC112PWR	125 °C	-55 °C	4 çA	10 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type	0.173 in	16-TSSOP	4.4 mm	1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-TSSOP	Complementary
Texas Instruments CD74HC112PWT	125 °C	-55 °C	4 çA	10 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type	0.173 in	16-TSSOP	4.4 mm	1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-TSSOP	Complementary
Texas Instruments SN74HC112DT			4 çA	3 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type	0.154 in	16-SOIC	3.9 mm	1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-SOIC	Complementary	85 °C	-40 °C	21 ns
Texas Instruments SN74HC112D			4 çA	3 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type	0.154 in	16-SOIC	3.9 mm	1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-SOIC	Complementary	85 °C	-40 °C	21 ns
Texas Instruments CD74HC112MT	125 °C	-55 °C	4 çA	10 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type	0.154 in	16-SOIC	3.9 mm	1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-SOIC	Complementary
Texas Instruments SN74HC112N			4 çA	3 pF	2	Through Hole	60 MHz	Reset Set(Preset)	JK Type		16-DIP		1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-PDIP	Complementary	85 °C	-40 °C	13 ns	0.3 in	7.62 mm
Texas Instruments CD74HC112NSR	125 °C	-55 °C	4 çA	10 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type		16-SOIC		1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-SO	Complementary				0.209 "	5.3 mm
Texas Instruments SN74HC112DR			4 çA	3 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type	0.154 in	16-SOIC	3.9 mm	1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-SOIC	Complementary	85 °C	-40 °C	21 ns

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.10
		10	$ 0.99
		40	$ 0.94
Texas Instruments	TUBE	1	$ 0.82
		100	$ 0.63
		250	$ 0.46
		1000	$ 0.33

Description

General part information

CD74HC112 Series

The SNx4HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high.

Documents

Technical documentation and resources

SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. I)

Data sheet

Signal Switch Data Book (Rev. A)

User guide

Input and Output Characteristics of Digital Integrated Circuits

Application note

SN74HC112D

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SN74HC112D

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Technical Specifications

CD74HC112 Series

Pricing

Description

CD74HC112 Series

Documents

Power-Up Behavior of Clocked Devices (Rev. B)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

HCMOS Design Considerations (Rev. A)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Designing With Logic (Rev. C)

Live Insertion

CMOS Power Consumption and CPD Calculation (Rev. B)

Logic Guide (Rev. AB)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

SN54/74HCT CMOS Logic Family Applications and Restrictions

LOGIC Pocket Data Book (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. I)

Signal Switch Data Book (Rev. A)

Input and Output Characteristics of Digital Integrated Circuits

CD74HC112 Series