CD74HC112 Series

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset

Catalog

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset

Part	Operating Temperature [Max]	Operating Temperature [Min]	Current - Quiescent (Iq)	Input Capacitance	Number of Elements	Mounting Type	Clock Frequency	Function	Type	Package / Case [x]	Package / Case	Package / Case [y]	Number of Bits per Element	Trigger Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Output Type	Operating Temperature [Max]	Operating Temperature [Min]	Max Propagation Delay @ V, Max CL	Package / Case	Package / Case
Texas Instruments CD74HC112PWR	125 °C	-55 °C	4 çA	10 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type	0.173 in	16-TSSOP	4.4 mm	1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-TSSOP	Complementary
Texas Instruments CD74HC112PWT	125 °C	-55 °C	4 çA	10 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type	0.173 in	16-TSSOP	4.4 mm	1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-TSSOP	Complementary
Texas Instruments SN74HC112DT			4 çA	3 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type	0.154 in	16-SOIC	3.9 mm	1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-SOIC	Complementary	85 °C	-40 °C	21 ns
Texas Instruments SN74HC112D			4 çA	3 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type	0.154 in	16-SOIC	3.9 mm	1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-SOIC	Complementary	85 °C	-40 °C	21 ns
Texas Instruments CD74HC112MT	125 °C	-55 °C	4 çA	10 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type	0.154 in	16-SOIC	3.9 mm	1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-SOIC	Complementary
Texas Instruments SN74HC112N			4 çA	3 pF	2	Through Hole	60 MHz	Reset Set(Preset)	JK Type		16-DIP		1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-PDIP	Complementary	85 °C	-40 °C	13 ns	0.3 in	7.62 mm
Texas Instruments CD74HC112NSR	125 °C	-55 °C	4 çA	10 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type		16-SOIC		1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-SO	Complementary				0.209 "	5.3 mm
Texas Instruments SN74HC112DR			4 çA	3 pF	2	Surface Mount	60 MHz	Reset Set(Preset)	JK Type	0.154 in	16-SOIC	3.9 mm	1	Negative Edge	5.2 mA	5.2 mA	2 V	6 V	16-SOIC	Complementary	85 °C	-40 °C	21 ns

Catalog

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset

Key Features

• Wide operating voltage range of 2V to 6VOutputs can drive up to 10 LSTTL loadsLow power consumption, 40µA max ICCTypical tpd = 13ns±4mA output drive at 5VLow input current of 1µA maxWide operating voltage range of 2V to 6VOutputs can drive up to 10 LSTTL loadsLow power consumption, 40µA max ICCTypical tpd = 13ns±4mA output drive at 5VLow input current of 1µA max

Description

The SNx4HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high. The SNx4HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high.