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SOIC (D)
Integrated Circuits (ICs)

SN74LVC112AD

Active
Texas Instruments

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsLogic Guide (Rev. AB)Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices+26
SOIC (D)
Integrated Circuits (ICs)

SN74LVC112AD

Active
Texas Instruments

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

Deep-Dive with AI

DocumentsLogic Guide (Rev. AB)Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices+26

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVC112AD
Clock Frequency150 MHz
Current - Output High, Low24 mA
Current - Quiescent (Iq)10 µA
FunctionReset, Set(Preset)
Input Capacitance4.5 pF
Max Propagation Delay @ V, Max CL5.9 ns
Mounting TypeSurface Mount
Number of Bits per Element1
Number of Elements2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeComplementary
Package / Case16-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Supplier Device Package16-SOIC
Trigger TypeNegative Edge
TypeJK Type
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]1.65 V

SN74LVC112A Series

Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset

PartTypeTrigger TypeClock FrequencyPackage / CasePackage / CasePackage / CaseOperating Temperature [Max]Operating Temperature [Min]Current - Output High, LowSupplier Device PackageCurrent - Quiescent (Iq)Mounting TypeOutput TypeNumber of ElementsNumber of Bits per ElementMax Propagation Delay @ V, Max CLFunctionVoltage - Supply [Min]Voltage - Supply [Max]Input CapacitancePackage / Case [x]Package / Case [y]Package / Case [custom]Package / Case [custom]
CD4555BE
Texas Instruments
SN74LVC112ANS
JK Type
Negative Edge
150 MHz
0.209 "
16-SOIC
5.3 mm
85 °C
-40 °C
24 mA
16-SO
10 µA
Surface Mount
Complementary
2
1
5.9 ns
Reset
Set(Preset)
1.65 V
3.6 V
4.5 pF
SOIC (D)
Texas Instruments
SN74LVC112ADR
JK Type
Negative Edge
150 MHz
16-SOIC
85 °C
-40 °C
24 mA
16-SOIC
10 µA
Surface Mount
Complementary
2
1
5.9 ns
Reset
Set(Preset)
1.65 V
3.6 V
4.5 pF
0.154 in
3.9 mm
16-TSSOP
Texas Instruments
SN74LVC112APWR
JK Type
Negative Edge
150 MHz
16-TSSOP
85 °C
-40 °C
24 mA
16-TSSOP
10 µA
Surface Mount
Complementary
2
1
5.9 ns
Reset
Set(Preset)
1.65 V
3.6 V
4.5 pF
0.173 in
4.4 mm
TSSOP (PW)
Texas Instruments
SN74LVC112APW
JK Type
Negative Edge
150 MHz
16-TSSOP
85 °C
-40 °C
24 mA
16-TSSOP
10 µA
Surface Mount
Complementary
2
1
5.9 ns
Reset
Set(Preset)
1.65 V
3.6 V
4.5 pF
0.173 in
4.4 mm
SOIC (D)
Texas Instruments
SN74LVC112AD
JK Type
Negative Edge
150 MHz
16-SOIC
85 °C
-40 °C
24 mA
16-SOIC
10 µA
Surface Mount
Complementary
2
1
5.9 ns
Reset
Set(Preset)
1.65 V
3.6 V
4.5 pF
0.154 in
3.9 mm
16 SO
Texas Instruments
SN74LVC112ANSR
JK Type
Negative Edge
150 MHz
0.209 "
16-SOIC
5.3 mm
85 °C
-40 °C
24 mA
16-SO
10 µA
Surface Mount
Complementary
2
1
5.9 ns
Reset
Set(Preset)
1.65 V
3.6 V
4.5 pF
SN74LV123ADGVR
Texas Instruments
SN74LVC112ADGVRG4
JK Type
Negative Edge
150 MHz
16-TFSOP
85 °C
-40 °C
24 mA
16-TVSOP
10 µA
Surface Mount
Complementary
2
1
5.9 ns
Reset
Set(Preset)
1.65 V
3.6 V
4.5 pF
0.173 in
4.4 mm
16 SOIC
Texas Instruments
SN74LVC112ADT
JK Type
Negative Edge
150 MHz
16-SOIC
85 °C
-40 °C
24 mA
16-SOIC
10 µA
Surface Mount
Complementary
2
1
5.9 ns
Reset
Set(Preset)
1.65 V
3.6 V
4.5 pF
0.154 in
3.9 mm
TVSOP (DGV)
Texas Instruments
SN74LVC112ADGVR
JK Type
Negative Edge
150 MHz
16-TFSOP
85 °C
-40 °C
24 mA
16-TVSOP
10 µA
Surface Mount
Complementary
2
1
5.9 ns
Reset
Set(Preset)
1.65 V
3.6 V
4.5 pF
0.173 in
4.4 mm
16-SSOP
Texas Instruments
SN74LVC112ADBR
JK Type
Negative Edge
150 MHz
16-SSOP
85 °C
-40 °C
24 mA
16-SSOP
10 µA
Surface Mount
Complementary
2
1
5.9 ns
Reset
Set(Preset)
1.65 V
3.6 V
4.5 pF
0.209 in
5.3 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.93
10$ 0.83
40$ 0.79
120$ 0.65
280$ 0.60
520$ 0.53
1000$ 0.49
Texas InstrumentsTUBE 1$ 1.14
100$ 0.77
250$ 0.60
1000$ 0.40

Description

General part information

SN74LVC112A Series

This dual negative-edge-triggered J-K flip-flop is designed for 1.65V to 3.6V VCC operation.

This dual negative-edge-triggered J-K flip-flop is designed for 1.65V to 3.6V VCC operation.

Documents

Technical documentation and resources

Logic Guide (Rev. AB)

Selection guide

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Application note

Input and Output Characteristics of Digital Integrated Circuits

Application note

TI IBIS File Creation, Validation, and Distribution Processes

Application note

Texas Instruments Little Logic Application Report

Application note

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Application note

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Application note

Low-Voltage Logic (LVC) Designer's Guide

Design guide

Little Logic Guide 2018 (Rev. G)

Selection guide

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Application note

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Application note

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

Understanding Advanced Bus-Interface Products Design Guide

Application note

LVC Characterization Information

Application note

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

Standard Linear & Logic for PCs, Servers & Motherboards

More literature

Signal Switch Data Book (Rev. A)

User guide

Live Insertion

Application note

Power-Up Behavior of Clocked Devices (Rev. B)

Application note

CMOS Power Consumption and CPD Calculation (Rev. B)

Application note

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

More literature

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

User guide

Selecting the Right Level Translation Solution (Rev. A)

Application note

SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop With Clear and Preset datasheet (Rev. N)

Data sheet

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Application note

LOGIC Pocket Data Book (Rev. B)

User guide

Design Summary for WCSP Little Logic (Rev. B)

Product overview

How to Select Little Logic (Rev. A)

Application note