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TSSOP (PW)
Integrated Circuits (ICs)

SN74LVC112APW

Active
Texas Instruments

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsImplications of Slow or Floating CMOS Inputs (Rev. E)LVC Characterization Information+26
TSSOP (PW)
Integrated Circuits (ICs)

SN74LVC112APW

Active
Texas Instruments

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

Deep-Dive with AI

DocumentsImplications of Slow or Floating CMOS Inputs (Rev. E)LVC Characterization Information+26

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVC112APW
Clock Frequency150 MHz
Current - Output High, Low24 mA
Current - Quiescent (Iq)10 µA
FunctionReset, Set(Preset)
Input Capacitance4.5 pF
Max Propagation Delay @ V, Max CL5.9 ns
Mounting TypeSurface Mount
Number of Bits per Element1
Number of Elements2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeComplementary
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Supplier Device Package16-TSSOP
Trigger TypeNegative Edge
TypeJK Type
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]1.65 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.93
10$ 0.83
90$ 0.65
270$ 0.60
540$ 0.53
1080$ 0.49
Texas InstrumentsTUBE 1$ 1.14
100$ 0.77
250$ 0.60
1000$ 0.40

Description

General part information

SN74LVC112A Series

This dual negative-edge-triggered J-K flip-flop is designed for 1.65V to 3.6V VCC operation.

This dual negative-edge-triggered J-K flip-flop is designed for 1.65V to 3.6V VCC operation.

Documents

Technical documentation and resources

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

LVC Characterization Information

Application note

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Application note

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Application note

Understanding Advanced Bus-Interface Products Design Guide

Application note

CMOS Power Consumption and CPD Calculation (Rev. B)

Application note

Standard Linear & Logic for PCs, Servers & Motherboards

More literature

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Application note

Signal Switch Data Book (Rev. A)

User guide

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Application note

How to Select Little Logic (Rev. A)

Application note

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Application note

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

More literature

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

User guide

Input and Output Characteristics of Digital Integrated Circuits

Application note

SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop With Clear and Preset datasheet (Rev. N)

Data sheet

Little Logic Guide 2018 (Rev. G)

Selection guide

LOGIC Pocket Data Book (Rev. B)

User guide

Low-Voltage Logic (LVC) Designer's Guide

Design guide

Logic Guide (Rev. AB)

Selection guide

Design Summary for WCSP Little Logic (Rev. B)

Product overview

Power-Up Behavior of Clocked Devices (Rev. B)

Application note

Live Insertion

Application note

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Application note

Selecting the Right Level Translation Solution (Rev. A)

Application note

TI IBIS File Creation, Validation, and Distribution Processes

Application note

Texas Instruments Little Logic Application Report

Application note