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20-pin (PW) package image
Integrated Circuits (ICs)

SN74HCT240PWT

Obsolete
Texas Instruments

8-CH, 4.5V TO 5.5V INVERTERS WITH TTL-COMPATIBLE CMOS INPUTS AND 3-STATE OUTPUTS

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20-pin (PW) package image
Integrated Circuits (ICs)

SN74HCT240PWT

Obsolete
Texas Instruments

8-CH, 4.5V TO 5.5V INVERTERS WITH TTL-COMPATIBLE CMOS INPUTS AND 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74HCT240PWT
Current - Output High, Low [custom]6 mA
Current - Output High, Low [custom]6 mA
Logic TypeInverting, Buffer
Mounting TypeSurface Mount
Number of Bits per Element4
Number of Elements2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output Type3-State
Package / Case20-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Supplier Device Package20-TSSOP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 1.27
10$ 1.14
25$ 1.08
100$ 0.89
Digi-Reel® 1$ 1.27
10$ 1.14
25$ 1.08
100$ 0.89
Tape & Reel (TR) 250$ 0.83
500$ 0.73
1250$ 0.58
2500$ 0.54
6250$ 0.51
12500$ 0.49
Texas InstrumentsSMALL T&R 1$ 0.94
100$ 0.72
250$ 0.53
1000$ 0.38

Description

General part information

SN74HCT240 Series

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HCT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HCT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.