
SN74LVC1G80DBVRG4
UnknownSINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
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SN74LVC1G80DBVRG4
UnknownSINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LVC1G80DBVRG4 |
|---|---|
| Clock Frequency | 160 MHz |
| Current - Output High, Low [x] | 32 mA |
| Current - Output High, Low [y] | 32 mA |
| Current - Quiescent (Iq) | 10 µA |
| Function | Standard |
| Input Capacitance | 3.5 pF |
| Max Propagation Delay @ V, Max CL | 4.5 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | 1.81 mOhm |
| Package / Case | SC-74A, SOT-753 |
| Supplier Device Package | SOT-23-5 |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.47 | |
| 10 | $ 0.39 | |||
| 25 | $ 0.35 | |||
| 100 | $ 0.26 | |||
| 250 | $ 0.24 | |||
| 500 | $ 0.20 | |||
| 1000 | $ 0.15 | |||
| Digi-Reel® | 1 | $ 0.47 | ||
| 10 | $ 0.39 | |||
| 25 | $ 0.35 | |||
| 100 | $ 0.26 | |||
| 250 | $ 0.24 | |||
| 500 | $ 0.20 | |||
| 1000 | $ 0.15 | |||
| Tape & Reel (TR) | 6000 | $ 0.13 | ||
| 15000 | $ 0.12 | |||
| 30000 | $ 0.11 | |||
| 75000 | $ 0.10 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.23 | |
| 100 | $ 0.16 | |||
| 250 | $ 0.12 | |||
| 1000 | $ 0.08 | |||
Description
General part information
SN74LVC1G80 Series
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
When data at the data (D) input meets the setup time requirement, the data is transferred to theQoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.
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Documents
Technical documentation and resources