
SN74LV32ATPWRQ1
ObsoleteOR GATE 4-ELEMENT 2-IN CMOS AUTOMOTIVE AEC-Q100 14-PIN TSSOP T/R
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SN74LV32ATPWRQ1
ObsoleteOR GATE 4-ELEMENT 2-IN CMOS AUTOMOTIVE AEC-Q100 14-PIN TSSOP T/R
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LV32ATPWRQ1 |
|---|---|
| Current - Output High, Low [custom] | 12 mA |
| Current - Output High, Low [custom] | 12 mA |
| Current - Quiescent (Max) [Max] | 20 µA |
| Grade | Automotive |
| Input Logic Level - High | 1.5 V |
| Input Logic Level - Low | 0.5 V |
| Logic Type | OR Gate |
| Max Propagation Delay @ V, Max CL | 7.5 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 4 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 105 ░C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 14-TSSOP |
| Package / Case [custom] | 0.173 " |
| Package / Case [custom] | 4.4 mm |
| Qualification | AEC-Q100 |
| Supplier Device Package | 14-TSSOP |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
SN74LV32A-EP Series
This quadruple 2-input positive-OR gate is designed for 2-V to 5.5-V VCCoperation.
The SN74LV32A-EP performs the Boolean function Y = A + B or Y = (A\ • B\)\ in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Documents
Technical documentation and resources
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