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8406201FA
Integrated Circuits (ICs)

8406201FA

Active
Texas Instruments

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

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Search across all available documentation for this part.

DocumentsDatasheetLOGIC Pocket Data Book (Rev. B)+12
8406201FA
Integrated Circuits (ICs)

8406201FA

Active
Texas Instruments

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

Deep-Dive with AI

DocumentsDatasheetLOGIC Pocket Data Book (Rev. B)+12

Technical Specifications

Parameters and characteristics for this part

Specification8406201FA
Circuit1 x 3:8
Current - Output High, Low [custom]5.2 mA
Current - Output High, Low [custom]5.2 mA
Independent Circuits1
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case16-CFlatPack
TypeDecoder/Demultiplexer
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V
Voltage Supply SourceSingle Supply

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Texas InstrumentsTUBE 1$ 42.80
100$ 37.38
250$ 28.82
1000$ 25.78

Description

General part information

SN54HC138 Series

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.