
CLVC574AQDWRG4Q1
ActiveFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT AUTOMOTIVE AEC-Q100 20-PIN SOIC T/R
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CLVC574AQDWRG4Q1
ActiveFLIP FLOP D-TYPE BUS INTERFACE POS-EDGE 3-ST 1-ELEMENT AUTOMOTIVE AEC-Q100 20-PIN SOIC T/R
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Technical Specifications
Parameters and characteristics for this part
| Specification | CLVC574AQDWRG4Q1 |
|---|---|
| Clock Frequency | 150 MHz |
| Current - Output High, Low | 24 mA |
| Current - Quiescent (Iq) | 10 µA |
| Function | Standard |
| Grade | Automotive |
| Input Capacitance | 4 pF |
| Max Propagation Delay @ V, Max CL | 7 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 20-SOIC |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Qualification | AEC-Q100 |
| Supplier Device Package | 20-SOIC |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.02 | |
| 10 | $ 0.92 | |||
| 25 | $ 0.87 | |||
| 100 | $ 0.71 | |||
| 250 | $ 0.67 | |||
| 500 | $ 0.59 | |||
| 1000 | $ 0.47 | |||
| Digi-Reel® | 1 | $ 1.02 | ||
| 10 | $ 0.92 | |||
| 25 | $ 0.87 | |||
| 100 | $ 0.71 | |||
| 250 | $ 0.67 | |||
| 500 | $ 0.59 | |||
| 1000 | $ 0.47 | |||
| Tape & Reel (TR) | 2000 | $ 0.38 | ||
| LCSC | Piece | 1 | $ 0.44 | |
| 200 | $ 0.17 | |||
| 500 | $ 0.17 | |||
| 1000 | $ 0.16 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.76 | |
| 100 | $ 0.58 | |||
| 250 | $ 0.43 | |||
| 1000 | $ 0.31 | |||
Description
General part information
SN74LVC574A-Q1 Series
The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation, and the SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCCoperation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
Documents
Technical documentation and resources