Specification	74LVC2G125DCUTG4

Current - Output High, Low [x]	32 mA
Current - Output High, Low [y]	32 mA
Logic Type	Buffer, Non-Inverting
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	3-State
Package / Case	8-VFSOP
Package / Case [y]	2.3 mm
Package / Case [y]	0.091 in
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	1.65 V

SN74LVC2G125 Series

2-ch, 1.65-V to 5.5-V buffers with 3-state outputs

Part	Number of Bits per Element	Mounting Type	Output Type	Operating Temperature [Min]	Operating Temperature [Max]	Number of Elements	Voltage - Supply [Max]	Voltage - Supply [Min]	Logic Type	Current - Output High, Low [y]	Current - Output High, Low [x]	Package / Case [y]	Package / Case	Package / Case [y]	Supplier Device Package [y]	Supplier Device Package	Supplier Device Package [x]
Texas Instruments 74LVC2G125DCUTG4	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in
Texas Instruments 74LVC2G125DCURG4	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in
Texas Instruments 74LVC2G125DCURE4	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in
Texas Instruments SN74LVC2G125DCUR	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in
Texas Instruments SN74LVC2G125YEPR	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA		8-XFBGA DSBGA		0.9	8-DSBGA (1.9x0.9)	1.9
Texas Instruments 74LVC2G125DCTRE4	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA					SM8
Texas Instruments SN74LVC2G125DCUR-S	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in
Texas Instruments SN74LVC2G125DCT3	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA					SM8
Texas Instruments 74LVC2G125DCTR-P2	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA					SM8
Texas Instruments 74LVC2G125DCUTE4	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	250	$ 0.88
		500	$ 0.78
		1250	$ 0.61
		2500	$ 0.57
		6250	$ 0.54
		12500	$ 0.52
Texas Instruments	SMALL T&R	1	$ 1.16
		100	$ 0.79
		250	$ 0.61
		1000	$ 0.41

Description

General part information

SN74LVC2G125 Series

The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCCoperation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Documents

Technical documentation and resources

Logic Guide (Rev. AB)

Selection guide

Enabling Optimal Solar Inverter Power Stage Designs with Logic

Application brief

SN74LVC2G125 Dual Bus Buffer Gate With 3-State Outputs datasheet (Rev. Q)

74LVC2G125DCUTG4

Deep-Dive with AI

74LVC2G125DCUTG4

Deep-Dive with AI

Technical Specifications

SN74LVC2G125 Series

Pricing

Description

SN74LVC2G125 Series

Documents

Logic Guide (Rev. AB)

Enabling Optimal Solar Inverter Power Stage Designs with Logic

SN74LVC2G125 Dual Bus Buffer Gate With 3-State Outputs datasheet (Rev. Q)

Low-Voltage Logic (LVC) Designer's Guide

Input and Output Characteristics of Digital Integrated Circuits

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Standard Linear & Logic for PCs, Servers & Motherboards

Implications of Slow or Floating CMOS Inputs (Rev. E)

How to Select Little Logic (Rev. A)

TI IBIS File Creation, Validation, and Distribution Processes

CMOS Power Consumption and CPD Calculation (Rev. B)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Signal Switch Data Book (Rev. A)

Selecting the Right Level Translation Solution (Rev. A)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Texas Instruments Little Logic Application Report

LVC Characterization Information

LOGIC Pocket Data Book (Rev. B)

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Understanding Advanced Bus-Interface Products Design Guide

Little Logic Guide 2018 (Rev. G)

Live Insertion

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

Design Summary for WCSP Little Logic (Rev. B)

SN74LVC2G125 Series