CD74HC4017QPWRQ1
ObsoleteCOUNTER/DIVIDER SINGLE 5-BIT DECADE UP AUTOMOTIVE AEC-Q100 16-PIN TSSOP T/R
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CD74HC4017QPWRQ1
ObsoleteCOUNTER/DIVIDER SINGLE 5-BIT DECADE UP AUTOMOTIVE AEC-Q100 16-PIN TSSOP T/R
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HC4017QPWRQ1 |
|---|---|
| Count Rate | 35 MHz |
| Direction | Up |
| Grade | Automotive |
| Logic Type | Counter, Decade |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 10 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 16-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Qualification | AEC-Q100 |
| Reset | Asynchronous |
| Supplier Device Package | 16-TSSOP |
| Timing | Synchronous |
| Trigger Type | Negative, Positive |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
CD74HC4017-EP Series
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
Documents
Technical documentation and resources
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