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16-DIP SOT38-1
Integrated Circuits (ICs)

CD74HC4017EG4

Unknown
Texas Instruments

IC DECADE COUNTER 10BIT 16DIP

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16-DIP SOT38-1
Integrated Circuits (ICs)

CD74HC4017EG4

Unknown
Texas Instruments

IC DECADE COUNTER 10BIT 16DIP

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationCD74HC4017EG4
Count Rate35 MHz
DirectionUp
Logic TypeCounter, Decade
Mounting TypeThrough Hole
Number of Bits per Element10
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case0.3 in
Package / Case16-DIP
Package / Case7.62 mm
ResetAsynchronous
Supplier Device Package16-PDIP
TimingSynchronous
Trigger TypeNegative, Positive
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1225$ 0.33

Description

General part information

CD74HC4017-EP Series

The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.

The device can drive up to ten low-power Schottky equivalent loads.

The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.

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