
CLVC573AQDWRG4Q1
ActiveAUTOMOTIVE CATALOG OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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CLVC573AQDWRG4Q1
ActiveAUTOMOTIVE CATALOG OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | CLVC573AQDWRG4Q1 |
|---|---|
| Circuit [custom] | 8 |
| Circuit [custom] | 8 |
| Current - Output High, Low | 24 mA |
| Delay Time - Propagation | 1 ns |
| Grade | Automotive |
| Independent Circuits | 1 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State |
| Package / Case | 20-SOIC |
| Package / Case [y] | 0.295 in |
| Package / Case [y] | 7.5 mm |
| Qualification | AEC-Q100 |
| Supplier Device Package | 20-SOIC |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.02 | |
| 10 | $ 0.92 | |||
| 25 | $ 0.87 | |||
| 100 | $ 0.71 | |||
| 250 | $ 0.67 | |||
| 500 | $ 0.59 | |||
| 1000 | $ 0.47 | |||
| Digi-Reel® | 1 | $ 1.02 | ||
| 10 | $ 0.92 | |||
| 25 | $ 0.87 | |||
| 100 | $ 0.71 | |||
| 250 | $ 0.67 | |||
| 500 | $ 0.59 | |||
| 1000 | $ 0.47 | |||
| Tape & Reel (TR) | 2000 | $ 0.33 | ||
| 4000 | $ 0.37 | |||
| 6000 | $ 0.36 | |||
| 10000 | $ 0.36 | |||
| 14000 | $ 0.35 | |||
| 20000 | $ 0.35 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.75 | |
| 100 | $ 0.51 | |||
| 250 | $ 0.39 | |||
| 1000 | $ 0.26 | |||
Description
General part information
SN74LVC573A-Q1 Series
The SN74LVC573A-EP octal transparent D-type latch is designed for 2.7-V to 3.6-V VCCoperation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.
Documents
Technical documentation and resources