Integrated Circuits (ICs)

SN74LVC573APWR

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Texas Instruments

TRANSPARENT LATCH, D-TYPE, TSSOP-20

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Integrated Circuits (ICs)

SN74LVC573APWR

Active

Texas Instruments

TRANSPARENT LATCH, D-TYPE, TSSOP-20

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DocumentsDatasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74LVC573APWR

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low	24 mA
Delay Time - Propagation	2 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	20-TSSOP
Package / Case [x]	0.173 in
Package / Case [y]	4.4 mm
Supplier Device Package	20-TSSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	1.65 V

SN74LVC573A-Q1 Series

Automotive Catalog Octal Transparent D-Type Latches With 3-State Outputs

Part	Circuit [custom]	Circuit [custom]	Current - Output High, Low	Package / Case	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Independent Circuits	Logic Type	Delay Time - Propagation	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Output Type	Package / Case [y]	Package / Case [x]	Package / Case [y]	Grade	Qualification
Texas Instruments SN74LVC573AZQNR	8	8	24 mA	20-VFBGA	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-BGA MICROSTAR JUNIOR (4x3)	Tri-State
Texas Instruments SN74LVC573APWRG4	8	8	24 mA	20-TSSOP	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-TSSOP	Tri-State	4.4 mm	0.173 in
Texas Instruments SN74LVC573AQPWREP	8	8	24 mA	20-TSSOP	Surface Mount	2 V	3.6 V	1	D-Type Transparent Latch	1 ns	125 °C	-40 °C	20-TSSOP	Tri-State	4.4 mm	0.173 in
Texas Instruments SN74LVC573ADWRG4	8	8	24 mA	20-SOIC	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-SOIC	Tri-State	0.295 in		7.5 mm
Texas Instruments SN74LVC573APWG4	8	8	24 mA	20-TSSOP	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-TSSOP	Tri-State	4.4 mm	0.173 in
Texas Instruments SN74LVC573APW	8	8	24 mA	20-TSSOP	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-TSSOP	Tri-State	4.4 mm	0.173 in
Texas Instruments SN74LVC573APWR	8	8	24 mA	20-TSSOP	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-TSSOP	Tri-State	4.4 mm	0.173 in
Texas Instruments SN74LVC573ARGYR	8	8	24 mA	20-VFQFN Exposed Pad	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-VQFN (3.5x4.5)	Tri-State
Texas Instruments SN74LVC573ADW	8	8	24 mA	20-SOIC	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-SOIC	Tri-State	0.295 in		7.5 mm
Texas Instruments CLVC573AQDWRG4Q1	8	8	24 mA	20-SOIC	Surface Mount	2 V	3.6 V	1	D-Type Transparent Latch	1 ns	125 °C	-40 °C	20-SOIC	Tri-State	0.295 in		7.5 mm	Automotive	AEC-Q100

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.87
		10	$ 0.54
		25	$ 0.45
		100	$ 0.35
		250	$ 0.30
		500	$ 0.27
		1000	$ 0.24
	Digi-Reel®	1	$ 0.87
		10	$ 0.54
		25	$ 0.45
		100	$ 0.35
		250	$ 0.30
		500	$ 0.27
		1000	$ 0.24
	Tape & Reel (TR)	2000	$ 0.22
		4000	$ 0.21
		6000	$ 0.20
		10000	$ 0.19
		14000	$ 0.18
		20000	$ 0.18
		50000	$ 0.16
Newark	Each (Supplied on Cut Tape)	1	$ 0.53
		10	$ 0.50
		25	$ 0.48
		50	$ 0.46
		100	$ 0.44
		250	$ 0.42
		500	$ 0.41
		1000	$ 0.41

Description

General part information

SN74LVC573A-Q1 Series

The SN74LVC573A-EP octal transparent D-type latch is designed for 2.7-V to 3.6-V VCCoperation.

This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.

Documents

Technical documentation and resources