Specification	SN74LVC573AQPWREP

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low	24 mA
Delay Time - Propagation	1 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	20-TSSOP
Package / Case [x]	0.173 in
Package / Case [y]	4.4 mm
Supplier Device Package	20-TSSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	2 V

SN74LVC573A-Q1 Series

Automotive Catalog Octal Transparent D-Type Latches With 3-State Outputs

Part	Circuit [custom]	Circuit [custom]	Current - Output High, Low	Package / Case	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Independent Circuits	Logic Type	Delay Time - Propagation	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Output Type	Package / Case [y]	Package / Case [x]	Package / Case [y]	Grade	Qualification
Texas Instruments SN74LVC573AZQNR	8	8	24 mA	20-VFBGA	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-BGA MICROSTAR JUNIOR (4x3)	Tri-State
Texas Instruments SN74LVC573APWRG4	8	8	24 mA	20-TSSOP	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-TSSOP	Tri-State	4.4 mm	0.173 in
Texas Instruments SN74LVC573AQPWREP	8	8	24 mA	20-TSSOP	Surface Mount	2 V	3.6 V	1	D-Type Transparent Latch	1 ns	125 °C	-40 °C	20-TSSOP	Tri-State	4.4 mm	0.173 in
Texas Instruments SN74LVC573ADWRG4	8	8	24 mA	20-SOIC	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-SOIC	Tri-State	0.295 in		7.5 mm
Texas Instruments SN74LVC573APWG4	8	8	24 mA	20-TSSOP	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-TSSOP	Tri-State	4.4 mm	0.173 in
Texas Instruments SN74LVC573APW	8	8	24 mA	20-TSSOP	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-TSSOP	Tri-State	4.4 mm	0.173 in
Texas Instruments SN74LVC573APWR	8	8	24 mA	20-TSSOP	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-TSSOP	Tri-State	4.4 mm	0.173 in
Texas Instruments SN74LVC573ARGYR	8	8	24 mA	20-VFQFN Exposed Pad	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-VQFN (3.5x4.5)	Tri-State
Texas Instruments SN74LVC573ADW	8	8	24 mA	20-SOIC	Surface Mount	1.65 V	3.6 V	1	D-Type Transparent Latch	2 ns	85 °C	-40 °C	20-SOIC	Tri-State	0.295 in		7.5 mm
Texas Instruments CLVC573AQDWRG4Q1	8	8	24 mA	20-SOIC	Surface Mount	2 V	3.6 V	1	D-Type Transparent Latch	1 ns	125 °C	-40 °C	20-SOIC	Tri-State	0.295 in		7.5 mm	Automotive	AEC-Q100

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 2.48
		10	$ 2.23
		25	$ 2.10
		100	$ 1.79
		250	$ 1.68
		500	$ 1.47
		1000	$ 1.22
	Digi-Reel®	1	$ 2.48
		10	$ 2.23
		25	$ 2.10
		100	$ 1.79
		250	$ 1.68
		500	$ 1.47
		1000	$ 1.22
	Tape & Reel (TR)	2000	$ 1.14
		6000	$ 1.09
Texas Instruments	LARGE T&R	1	$ 1.87
		100	$ 1.54
		250	$ 1.11
		1000	$ 0.83

Description

General part information

SN74LVC573A-Q1 Series

The SN74LVC573A-EP octal transparent D-type latch is designed for 2.7-V to 3.6-V VCCoperation.

This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.

Documents

Technical documentation and resources

SN74LVC573AQPWREP

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SN74LVC573AQPWREP

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Technical Specifications

SN74LVC573A-Q1 Series

Pricing

Description

SN74LVC573A-Q1 Series

Documents

How to Select Little Logic (Rev. A)

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Logic Guide (Rev. AB)

Standard Linear & Logic for PCs, Servers & Motherboards

LOGIC Pocket Data Book (Rev. B)

LVC Characterization Information

Implications of Slow or Floating CMOS Inputs (Rev. E)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Signal Switch Data Book (Rev. A)

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Low-Voltage Logic (LVC) Designer's Guide

Input and Output Characteristics of Digital Integrated Circuits

Little Logic Guide 2018 (Rev. G)

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Power-Up Behavior of Clocked Devices (Rev. B)

Texas Instruments Little Logic Application Report

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Understanding Advanced Bus-Interface Products Design Guide

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

SN74LVC573A-EP datasheet (Rev. A)

Design Summary for WCSP Little Logic (Rev. B)

Live Insertion

Selecting the Right Level Translation Solution (Rev. A)

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

CMOS Power Consumption and CPD Calculation (Rev. B)

SN74LVC573A-Q1 Series