SN74LVC573A-Q1 Series
Automotive Catalog Octal Transparent D-Type Latches With 3-State Outputs
Manufacturer: Texas Instruments
Catalog
Automotive Catalog Octal Transparent D-Type Latches With 3-State Outputs
| Part | Circuit [custom] | Circuit [custom] | Current - Output High, Low | Package / Case | Mounting Type | Voltage - Supply [Min] | Voltage - Supply [Max] | Independent Circuits | Logic Type | Delay Time - Propagation | Operating Temperature [Max] | Operating Temperature [Min] | Supplier Device Package | Output Type | Package / Case [y] | Package / Case [x] | Package / Case [y] | Grade | Qualification |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
 Texas Instruments | 8 | 8 | 24 mA | 20-VFBGA | Surface Mount | 1.65 V | 3.6 V | 1 | D-Type Transparent Latch | 2 ns | 85 °C | -40 °C | 20-BGA MICROSTAR JUNIOR (4x3) | Tri-State | |||||
 Texas Instruments | 8 | 8 | 24 mA | 20-TSSOP | Surface Mount | 1.65 V | 3.6 V | 1 | D-Type Transparent Latch | 2 ns | 85 °C | -40 °C | 20-TSSOP | Tri-State | 4.4 mm | 0.173 in | |||
Texas Instruments | 8 | 8 | 24 mA | 20-TSSOP | Surface Mount | 2 V | 3.6 V | 1 | D-Type Transparent Latch | 1 ns | 125 °C | -40 °C | 20-TSSOP | Tri-State | 4.4 mm | 0.173 in | |||
 Texas Instruments | 8 | 8 | 24 mA | 20-SOIC | Surface Mount | 1.65 V | 3.6 V | 1 | D-Type Transparent Latch | 2 ns | 85 °C | -40 °C | 20-SOIC | Tri-State | 0.295 in | 7.5 mm | |||
Texas Instruments | 8 | 8 | 24 mA | 20-TSSOP | Surface Mount | 1.65 V | 3.6 V | 1 | D-Type Transparent Latch | 2 ns | 85 °C | -40 °C | 20-TSSOP | Tri-State | 4.4 mm | 0.173 in | |||
 Texas Instruments | 8 | 8 | 24 mA | 20-TSSOP | Surface Mount | 1.65 V | 3.6 V | 1 | D-Type Transparent Latch | 2 ns | 85 °C | -40 °C | 20-TSSOP | Tri-State | 4.4 mm | 0.173 in | |||
Texas Instruments | 8 | 8 | 24 mA | 20-TSSOP | Surface Mount | 1.65 V | 3.6 V | 1 | D-Type Transparent Latch | 2 ns | 85 °C | -40 °C | 20-TSSOP | Tri-State | 4.4 mm | 0.173 in | |||
 Texas Instruments | 8 | 8 | 24 mA | 20-VFQFN Exposed Pad | Surface Mount | 1.65 V | 3.6 V | 1 | D-Type Transparent Latch | 2 ns | 85 °C | -40 °C | 20-VQFN (3.5x4.5) | Tri-State | |||||
 Texas Instruments | 8 | 8 | 24 mA | 20-SOIC | Surface Mount | 1.65 V | 3.6 V | 1 | D-Type Transparent Latch | 2 ns | 85 °C | -40 °C | 20-SOIC | Tri-State | 0.295 in | 7.5 mm | |||
Texas Instruments | 8 | 8 | 24 mA | 20-SOIC | Surface Mount | 2 V | 3.6 V | 1 | D-Type Transparent Latch | 1 ns | 125 °C | -40 °C | 20-SOIC | Tri-State | 0.295 in | 7.5 mm | Automotive | AEC-Q100 |
Key Features
• Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of –40°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification PedigreeOperates From 2 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 6.9 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CSupports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)IoffSupports Partial-Power-Down Mode OperationComponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of –40°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification PedigreeOperates From 2 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 6.9 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CSupports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)IoffSupports Partial-Power-Down Mode OperationComponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
Description
AI
The SN74LVC573A-EP octal transparent D-type latch is designed for 2.7-V to 3.6-V VCCoperation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
The SN74LVC573A-EP octal transparent D-type latch is designed for 2.7-V to 3.6-V VCCoperation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.