SN74LV574ADBR
ActiveOCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
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SN74LV574ADBR
ActiveOCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LV574ADBR |
|---|---|
| Current - Output High, Low [custom] | 16 mA |
| Current - Output High, Low [custom] | 16 mA |
| Current - Quiescent (Iq) | 20 çA |
| Function | Standard |
| Input Capacitance | 1.8 pF |
| Max Propagation Delay @ V, Max CL | 10.6 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 20-SSOP |
| Supplier Device Package | 20-SSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.82 | |
| 10 | $ 0.51 | |||
| 25 | $ 0.43 | |||
| 100 | $ 0.33 | |||
| 250 | $ 0.28 | |||
| 500 | $ 0.26 | |||
| 1000 | $ 0.23 | |||
| Digi-Reel® | 1 | $ 0.82 | ||
| 10 | $ 0.51 | |||
| 25 | $ 0.43 | |||
| 100 | $ 0.33 | |||
| 250 | $ 0.28 | |||
| 500 | $ 0.26 | |||
| 1000 | $ 0.23 | |||
| Tape & Reel (TR) | 2000 | $ 0.18 | ||
| 6000 | $ 0.17 | |||
| 10000 | $ 0.16 | |||
| 50000 | $ 0.15 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.29 | |
| 100 | $ 0.22 | |||
| 250 | $ 0.16 | |||
| 1000 | $ 0.12 | |||
Description
General part information
SN74LV574A Series
The ’LV574A devices are octal edge-triggered D-type flip-flops designed for 2 V to 5.5 V VCCoperation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
Documents
Technical documentation and resources
