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Texas Instruments-CD74FCT244ATE Buffers and Line Drivers Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin PDIP Tube
Integrated Circuits (ICs)

SN74HC240NE4

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Texas Instruments

BUFFER/LINE DRIVER 8-CH INVERTING 3-ST CMOS 20-PIN PDIP TUBE

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Texas Instruments-CD74FCT244ATE Buffers and Line Drivers Buffer/Line Driver 8-CH Non-Inverting 3-ST CMOS 20-Pin PDIP Tube
Integrated Circuits (ICs)

SN74HC240NE4

Active
Texas Instruments

BUFFER/LINE DRIVER 8-CH INVERTING 3-ST CMOS 20-PIN PDIP TUBE

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74HC240NE4
Current - Output High, Low [custom]7.8 mA
Current - Output High, Low [custom]7.8 mA
Logic TypeInverting, Buffer
Mounting TypeThrough Hole
Number of Bits per Element4
Number of Elements2
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output Type3-State
Package / Case20-DIP
Package / Case7.62 mm
Package / Case0.3 in
Supplier Device Package20-PDIP
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1000$ 0.76

Description

General part information

SN74HC240 Series

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

Documents

Technical documentation and resources