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16-TSSOP
Integrated Circuits (ICs)

LMK00804BPW

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Texas Instruments

IC CLK BUFFER 2:4 350MHZ 16TSSOP

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16-TSSOP
Integrated Circuits (ICs)

LMK00804BPW

Active
Texas Instruments

IC CLK BUFFER 2:4 350MHZ 16TSSOP

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationLMK00804BPW
Differential - Input:OutputYes/No
Frequency - Max [Max]350 MHz
InputLVDS, LVHSTL, LVCMOS, LVPECL, LVTTL, HCSL, SSTL
Mounting TypeSurface Mount
Number of Circuits1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
OutputLVCMOS, LVTTL
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Ratio - Input:Output1:4
Supplier Device Package16-TSSOP
TypeFanout Buffer (Distribution)
Voltage - Supply [Max]3.465 V
Voltage - Supply [Min]1.425 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 6.66
10$ 6.02
92$ 4.98
276$ 4.76
552$ 4.34
1012$ 3.78
2576$ 3.64
NewarkEach 1$ 8.03
10$ 7.66
25$ 7.43
50$ 7.04
184$ 6.78
276$ 6.51
552$ 6.40

Description

General part information

LMK00804B-Q1 Series

The LMK00804B-Q1 is a high-performance clock fan-out buffer and level translator that can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs that can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or deasserted. The outputs are held in logic low state when the clock is disabled. The LMK00804B-Q1 can also distribute a low-jitter clock across four transceivers and can improve the overall target detection and resolution in a cascaded mmWave radar system.

The LMK00804B-Q1 is a high-performance clock fan-out buffer and level translator that can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs that can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or deasserted. The outputs are held in logic low state when the clock is disabled. The LMK00804B-Q1 can also distribute a low-jitter clock across four transceivers and can improve the overall target detection and resolution in a cascaded mmWave radar system.

Documents

Technical documentation and resources

No documents available