LMK00804B-Q1 Series

Automotive, 1.5-V to 3.3-V, 1-to-4 high-performance LVCMOS fanout buffer & level translator

Catalog

Automotive, 1.5-V to 3.3-V, 1-to-4 high-performance LVCMOS fanout buffer & level translator

Part	Operating Temperature [Min]	Operating Temperature [Max]	Frequency - Max [Max]	Grade	Voltage - Supply [Max]	Voltage - Supply [Min]	Type	Package / Case	Output	Supplier Device Package	Input	Number of Circuits	Ratio - Input:Output	Qualification	Differential - Input:Output	Mounting Type	Package / Case [x]	Package / Case [y]	Secondary Attributes	Function	Supplied Contents	Utilized IC / Part
Texas Instruments LMK00804BQWRGTRQ1	-40 °C	125 °C	350 MHz	Automotive	3.465 V	1.425 V	Fanout Buffer (Distribution) Translator	16-VFQFN Exposed Pad	LVCMOS LVTTL	16-VQFN (3x3)	HCSL LVCMOS LVDS LVHSTL LVPECL LVTTL SSTL	1	1:4	AEC-Q100	Yes/No	Surface Mount Wettable Flank
Texas Instruments LMK00804BPWR	-40 °C	85 °C	350 MHz		3.465 V	3.135 V	Fanout Buffer (Distribution) Multiplexer	16-TSSOP	LVCMOS LVTTL	16-TSSOP	HCSL LVCMOS LVDS LVHSTL LVPECL LVTTL SSTL	1	1:4		Yes/No	Surface Mount	0.173 in	4.4 mm
Texas Instruments LMK00804BEVM							Timing												SMA Connectors	Clock Buffer	Board(s)	LMK00804B
Texas Instruments LMK00804BPW	-40 °C	85 °C	350 MHz		3.465 V	1.425 V	Fanout Buffer (Distribution)	16-TSSOP	LVCMOS LVTTL	16-TSSOP	HCSL LVCMOS LVDS LVHSTL LVPECL LVTTL SSTL	1	1:4		Yes/No	Surface Mount	0.173 in	4.4 mm

Catalog

Automotive, 1.5-V to 3.3-V, 1-to-4 high-performance LVCMOS fanout buffer & level translator

Key Features

• AEC-Q100 qualified with the following results:Device temperature grade 1: –40°C to +125°C, TAFour LVCMOS/LVTTL outputs supporting 1.5-V to 3.3-V levelsAdditive jitter: 0.1-ps RMS (typical) at 40 MHzNoise floor: –168 dBc/Hz (typical) at 40 MHzOutput frequency: 350 MHz (maximum)Output skew: 35 ps (maximum)Part-to-part skew: 550 ps (maximum)Two selectable inputsCLK_P, CLK_N pair accepts LVPECL, LVDS, HCSL, SSTL, LVHSTL, or LVCMOS/LVTTLLVCMOS_CLK accepts LVCMOS/LVTTLSynchronous clock enableCore/output power supplies:3.3 V/3.3 V3.3 V/2.5 V3.3 V/1.8 V3.3 V/1.5 VPackage: 16-pin VQFNAEC-Q100 qualified with the following results:Device temperature grade 1: –40°C to +125°C, TAFour LVCMOS/LVTTL outputs supporting 1.5-V to 3.3-V levelsAdditive jitter: 0.1-ps RMS (typical) at 40 MHzNoise floor: –168 dBc/Hz (typical) at 40 MHzOutput frequency: 350 MHz (maximum)Output skew: 35 ps (maximum)Part-to-part skew: 550 ps (maximum)Two selectable inputsCLK_P, CLK_N pair accepts LVPECL, LVDS, HCSL, SSTL, LVHSTL, or LVCMOS/LVTTLLVCMOS_CLK accepts LVCMOS/LVTTLSynchronous clock enableCore/output power supplies:3.3 V/3.3 V3.3 V/2.5 V3.3 V/1.8 V3.3 V/1.5 VPackage: 16-pin VQFN

Description

The LMK00804B-Q1 is a high-performance clock fan-out buffer and level translator that can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs that can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or deasserted. The outputs are held in logic low state when the clock is disabled. The LMK00804B-Q1 can also distribute a low-jitter clock across four transceivers and can improve the overall target detection and resolution in a cascaded mmWave radar system. The LMK00804B-Q1 is a high-performance clock fan-out buffer and level translator that can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs that can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or deasserted. The outputs are held in logic low state when the clock is disabled. The LMK00804B-Q1 can also distribute a low-jitter clock across four transceivers and can improve the overall target detection and resolution in a cascaded mmWave radar system.