Specification	CLVC16373AMDLREP

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low	24 mA
Delay Time - Propagation	1.3 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Tri-State
Package / Case	48-BSSOP
Package / Case [y]	0.295 in
Package / Case [y]	7.5 mm
Supplier Device Package	48-SSOP
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	1.65 V

SN74LVC16373A-EP Series

Enhanced Product 16-Bit Transparent D-Type Latch With 3-State Outputs

Part	Independent Circuits	Delay Time - Propagation	Logic Type	Output Type	Operating Temperature [Min]	Operating Temperature [Max]	Current - Output High, Low	Mounting Type	Supplier Device Package	Circuit [custom]	Circuit [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case [y]	Package / Case	Package / Case [y]	Package / Case	Package / Case [custom]
Texas Instruments CLVC16373AMDLREP	1	1.3 ns	D-Type Transparent Latch	Tri-State	-55 °C	125 °C	24 mA	Surface Mount	48-SSOP	8	8	1.65 V	3.6 V	0.295 in	48-BSSOP	7.5 mm
Texas Instruments SN74LVC16373DGGR	2	2.1 ns	D-Type Transparent Latch	Tri-State	-40 °C	85 °C	24 mA	Surface Mount	48-TSSOP	8	8	1.65 V	3.6 V		48-TFSOP		0.24 in	6.1 mm
Texas Instruments 74LVC16373DGGRG4	2	2.1 ns	D-Type Transparent Latch	Tri-State	-40 °C	85 °C	24 mA	Surface Mount	48-TSSOP	8	8	1.65 V	3.6 V		48-TFSOP		0.24 in	6.1 mm
Texas Instruments SN74LVC16373ADLR	2	2.1 ns	D-Type Transparent Latch	Tri-State	-40 °C	85 °C	24 mA	Surface Mount	48-SSOP	8	8	1.65 V	3.6 V	0.295 in	48-BSSOP	7.5 mm
Texas Instruments SN74LVC16373AZQLR	2	2.1 ns	D-Type Transparent Latch	Tri-State	-40 °C	85 °C	24 mA	Surface Mount	56-BGA Microstar Junior (7x4.5)	8	8	1.65 V	3.6 V		56-VFBGA
Texas Instruments SN74LVC16373ADGVR	2	2.1 ns	D-Type Transparent Latch	Tri-State	-40 °C	85 °C	24 mA	Surface Mount		8	8	1.65 V	3.6 V		48-TFSOP		0.173 in 4.4 mm
Texas Instruments 74LVC16373DGGRE4	2	8 ns	D-Type Transparent Latch	Non-Inverted Tri-State	-40 °C	85 °C	24 mA	Surface Mount	48-TSSOP	8	8	1.65 V	3.6 V		48-TFSOP		0.24 in	6.1 mm
Texas Instruments SN74LVC16373ADLG4	2	2.1 ns	D-Type Transparent Latch	Tri-State	-40 °C	85 °C	24 mA	Surface Mount	48-SSOP	8	8	1.65 V	3.6 V	0.295 in	48-BSSOP	7.5 mm
Texas Instruments 74LVC16373ADGGRG4	2	2.1 ns	D-Type Transparent Latch	Tri-State	-40 °C	85 °C	24 mA	Surface Mount	48-TSSOP	8	8	1.65 V	3.6 V		48-TFSOP		0.24 in	6.1 mm
Texas Instruments 74LVC16373ADGVRE4	2	2.1 ns	D-Type Transparent Latch	Tri-State	-40 °C	85 °C	24 mA	Surface Mount		8	8	1.65 V	3.6 V		48-TFSOP		0.173 in 4.4 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 4.27
		10	$ 3.84
		25	$ 3.63
		100	$ 3.15
		250	$ 2.98
		500	$ 2.68
	Digi-Reel®	1	$ 4.27
		10	$ 3.84
		25	$ 3.63
		100	$ 3.15
		250	$ 2.98
		500	$ 2.68
	Tape & Reel (TR)	1000	$ 2.26
		2000	$ 2.15
Texas Instruments	LARGE T&R	1	$ 2.94
		100	$ 2.40
		250	$ 1.88
		1000	$ 1.60

Description

General part information

SN74LVC16373A-EP Series

This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCCoperation.

The SN74LVC16373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

Documents

Technical documentation and resources

LOGIC Pocket Data Book (Rev. B)

CLVC16373AMDLREP

Deep-Dive with AI

CLVC16373AMDLREP

Deep-Dive with AI

Technical Specifications

SN74LVC16373A-EP Series

Pricing

Description

SN74LVC16373A-EP Series

Documents

Low-Voltage Logic (LVC) Designer's Guide

SN74LVC16373A-EP datasheet

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

LOGIC Pocket Data Book (Rev. B)

Standard Linear & Logic for PCs, Servers & Motherboards

Understanding Advanced Bus-Interface Products Design Guide

LVC Characterization Information

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Signal Switch Data Book (Rev. A)

Texas Instruments Little Logic Application Report

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Power-Up Behavior of Clocked Devices (Rev. B)

Selecting the Right Level Translation Solution (Rev. A)

How to Select Little Logic (Rev. A)

Little Logic Guide 2018 (Rev. G)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Live Insertion

Design Summary for WCSP Little Logic (Rev. B)

Input and Output Characteristics of Digital Integrated Circuits

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Logic Guide (Rev. AB)

TI IBIS File Creation, Validation, and Distribution Processes

CMOS Power Consumption and CPD Calculation (Rev. B)

SN74LVC16373A-EP Series