Specification	SN74ABT125RGYR

Current - Output High, Low [custom]	64 mA
Current - Output High, Low [custom]	32 mA
Logic Type	Buffer, Non-Inverting
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	4
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	3-State
Package / Case	14-VFQFN Exposed Pad
Supplier Device Package	14-VQFN (3.5x3.5)
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74ABT125Q-Q1 Series

Automotive 4-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Part	Package / Case	Number of Elements	Operating Temperature [Max]	Operating Temperature [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Number of Bits per Element	Output Type	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Logic Type	Package / Case [x]	Package / Case [y]	Package / Case [custom]	Package / Case [custom]	Grade	Qualification	Current - Output High, Low	Package / Case	Package / Case
Texas Instruments SN74ABT125RGYR	14-VFQFN Exposed Pad	4	85 °C	-40 °C	64 mA	32 mA	1	3-State	Surface Mount	4.5 V	5.5 V	14-VQFN (3.5x3.5)	Buffer Non-Inverting
Texas Instruments SN74ABT125DG4	14-SOIC	4	85 °C	-40 °C	64 mA	32 mA	1	3-State	Surface Mount	4.5 V	5.5 V		Buffer Non-Inverting	0.154 in	3.9 mm
Texas Instruments SN74ABT125DR	14-SOIC	4	85 °C	-40 °C	64 mA	32 mA	1	3-State	Surface Mount	4.5 V	5.5 V		Buffer Non-Inverting	0.154 in	3.9 mm
Texas Instruments SN74ABT125PWE4	14-TSSOP	4	85 °C	-40 °C	64 mA	32 mA	1	3-State	Surface Mount	4.5 V	5.5 V	14-TSSOP	Buffer Non-Inverting			0.173 "	4.4 mm
Texas Instruments SN74ABT125QDRQ1	14-SOIC	4	125 °C	-40 °C			1	3-State	Surface Mount	4.5 V	5.5 V		Buffer Non-Inverting	0.154 in	3.9 mm			Automotive	AEC-Q100	16 mA 32 mA
Texas Instruments SN74ABT125DBR	14-SSOP	4	85 °C	-40 °C	64 mA	32 mA	1	3-State	Surface Mount	4.5 V	5.5 V	14-SSOP	Buffer Non-Inverting								5.3 mm	0.209 "
Texas Instruments SN74ABT125PWRG4	14-TSSOP	4	85 °C	-40 °C	64 mA	32 mA	1	3-State	Surface Mount	4.5 V	5.5 V	14-TSSOP	Buffer Non-Inverting			0.173 "	4.4 mm
Texas Instruments SN74ABT125DRG4	14-SOIC	4	85 °C	-40 °C	64 mA	32 mA	1	3-State	Surface Mount	4.5 V	5.5 V		Buffer Non-Inverting	0.154 in	3.9 mm
Texas Instruments SN74ABT125N	14-DIP	4	85 °C	-40 °C	64 mA	32 mA	1	3-State	Through Hole	4.5 V	5.5 V		Buffer Non-Inverting	0.3 "	7.62 mm
Texas Instruments SN74ABT125PWRE4	14-TSSOP	4	85 °C	-40 °C	64 mA	32 mA	1	3-State	Surface Mount	4.5 V	5.5 V	14-TSSOP	Buffer Non-Inverting			0.173 "	4.4 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.90
	Digi-Reel®	1	$ 0.90
	Tape & Reel (TR)	3000	$ 0.36
		6000	$ 0.35
		15000	$ 0.33
		30000	$ 0.32
Texas Instruments	LARGE T&R	1	$ 0.64
		100	$ 0.49
		250	$ 0.36
		1000	$ 0.26

Description

General part information

SN74ABT125Q-Q1 Series

The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.

These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Documents

Technical documentation and resources

SN74ABT125RGYR

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SN74ABT125RGYR

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Technical Specifications

SN74ABT125Q-Q1 Series

Pricing

Description

SN74ABT125Q-Q1 Series

Documents

Logic Guide

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)

SN54ABT125, SN74ABT125 datasheet (Rev. I)

TI IBIS File Creation, Validation, and Distribution Processes

Quad Flatpack No-Lead Logic Packages (Rev. D)

Selecting the Right Level Translation Solution (Rev. A)

Designing With Logic (Rev. C)

Input and Output Characteristics of Digital Integrated Circuits

Understanding Advanced Bus-Interface Products Design Guide

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Live Insertion

Advanced Bus Interface Logic Selection Guide

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

LOGIC Pocket Data Book (Rev. B)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)

SN74ABT125Q-Q1 Series