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Technical Specifications
Parameters and characteristics for this part
| Specification | EVAL-AD5684RSDZ |
|---|---|
| DAC Type | Voltage |
| Data Interface | SPI |
| Number of Bits | 12 bits |
| Number of DAC's | 4 |
| Settling Time | 5 µs |
| Supplied Contents | Board(s) |
| Utilized IC / Part | AD5684R |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
AD5684R Series
The AD5686/AD5684, a member of thenanoDAC+™ family, is a low power, quad, 16-/12-bit buffered voltage output DAC. The device includes a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5686/AD5684 also incorporate a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.The AD5686/AD5684 employ a versatile SPI interface that operates at clock rates up to 50 MHz, and all devices contain a VLOGICpin intended for 1.8 V/3 V/5 V logic.Product HighlightsHigh Relative Accuracy (INL): ±2 LSB maximumExcellent DC Performance.Total unadjusted error: ±0.1% of FSR maximumOffset error: ±1.5 mV maximumGain error: ±0.1% of FSR maximumTwo Package Options: 3 mm × 3 mm, 16-lead LFCSP and 16-lead TSSOPApplicationsDigital gain and offset adjustmentProgrammable attenuatorsProcess control (PLC I/O cards)Industrial automationData acquisition systems
Documents
Technical documentation and resources