Texas Instruments

The ADC08D502 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is specified to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA≤ +85°C) temperature range. The ADC08D502 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is specified to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA≤ +85°C) temperature range.

The ADC08DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC08DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems. The ADC08DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. At 5 GSPS, only four total lanes are required running at 12.5 Gbps or 16 lanes can be used to reduce the lane rate to 3.125 Gbps. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. The ADC08DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC08DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems. The ADC08DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. At 5 GSPS, only four total lanes are required running at 12.5 Gbps or 16 lanes can be used to reduce the lane rate to 3.125 Gbps. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications.

The ADC08DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that directly samples input frequencies from DC to above 10GHz. The ADC08DJ5200RF can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems. The ADC08DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers. Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. A programmable FIR filter allows on-chip equalization. The ADC08DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that directly samples input frequencies from DC to above 10GHz. The ADC08DJ5200RF can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems. The ADC08DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers. Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. A programmable FIR filter allows on-chip equalization.

The ADC08DL500 is a dual, low power, high performance, CMOS analog-to-digital converter. The ADC08DL500 digitizes signals to 8 bits of resolution at sample rates up to 500 MSPS. Consuming a typical 1.2 Watts in demultiplex mode at 500 MSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration schemes enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.2EffectiveNumber of Bits (ENOB) with a 125 MHz input signal and a 500 MHz sample rate while providing a10−18CodeErrorRate (C.E.R.) The converter typically consumes 3.3 mW in the Power Down Mode and is available in a lead-free 144-lead LQFP and operates over the modified Industrial (-40°C≤TA≤+70°C) temperature range. The ADC08DL500 is a dual, low power, high performance, CMOS analog-to-digital converter. The ADC08DL500 digitizes signals to 8 bits of resolution at sample rates up to 500 MSPS. Consuming a typical 1.2 Watts in demultiplex mode at 500 MSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration schemes enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.2EffectiveNumber of Bits (ENOB) with a 125 MHz input signal and a 500 MHz sample rate while providing a10−18CodeErrorRate (C.E.R.) The converter typically consumes 3.3 mW in the Power Down Mode and is available in a lead-free 144-lead LQFP and operates over the modified Industrial (-40°C≤TA≤+70°C) temperature range.

The ADC08L060 is a low-power, 8-bit, monolithic analog-to-digital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates of 10 MSPS to 60 MSPS while consuming just 0.65 mW per MHz of clock frequency, or 39 mW at 60 MSPS. Raising the PD pin puts the ADC08L060 into a Power Down mode where it consumes about 1 mW. The unique architecture achieves 7.6 Effective Bits. The ADC08L060 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08L060s reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 1.8V to 3V logic. The output coding is straight binary and the digital inputs (CLK and PD) are TTL/CMOS compatible. The ADC08L060 is offered in a 24-lead plastic package (TSSOP) and is specified over the industrial temperature range of −40°C to +85°C. The ADC08L060 is a low-power, 8-bit, monolithic analog-to-digital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates of 10 MSPS to 60 MSPS while consuming just 0.65 mW per MHz of clock frequency, or 39 mW at 60 MSPS. Raising the PD pin puts the ADC08L060 into a Power Down mode where it consumes about 1 mW. The unique architecture achieves 7.6 Effective Bits. The ADC08L060 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08L060s reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 1.8V to 3V logic. The output coding is straight binary and the digital inputs (CLK and PD) are TTL/CMOS compatible. The ADC08L060 is offered in a 24-lead plastic package (TSSOP) and is specified over the industrial temperature range of −40°C to +85°C.

ADC09xJ1300 is a family of quad, dual and single channel, 9-bit, 1.3GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300 ideally suited for suited for a variety of multi-channel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. ADC09xJ1300 is a family of quad, dual and single channel, 9-bit, 1.3GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300 ideally suited for suited for a variety of multi-channel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC09xJ1300-Q1 is a family of quad, dual and single channel, 9-bit, 1.3 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300-Q1 ideally suited for light detection and ranging (LiDAR) systems. ADC09xJ1300-Q1 is qualified for automotive applications. Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4GHz. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. ADC09xJ1300-Q1 is a family of quad, dual and single channel, 9-bit, 1.3 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300-Q1 ideally suited for light detection and ranging (LiDAR) systems. ADC09xJ1300-Q1 is qualified for automotive applications. Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4GHz. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC09xJ800 is a family of quad, dual and single channel, 9-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC09xJ800 ideally suited for a variety of multichannel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. ADC09xJ800 is a family of quad, dual and single channel, 9-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC09xJ800 ideally suited for a variety of multichannel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC09xJ800-Q1 is a family of quad, dual and single channel, 9-bit, 800MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC09xJ800-Q1 is qualified for automotive applications. Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4GHz. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. ADC09xJ800-Q1 is a family of quad, dual and single channel, 9-bit, 800MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC09xJ800-Q1 is qualified for automotive applications. Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4GHz. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.