Texas Instruments

The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0and S1). The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode. In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0and S1). The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode. In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The AEC-Q100 qualified 2N7001T-Q1 device is a single-bit buffered voltage signal converter that uses two separate configurable power-supply rails to up or down translate a unidirectional signal. The device is operational with both VCCAand VCCBsupplies down to 1.65 V and up to 3.60 V. VCCAdefines the input threshold voltage on the A input. VCCBdefines the output drive voltage on the B output. This device is fully specified for partial-power-down applications using the Ioffcurrent. The Ioffprotection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down. The VCCisolation feature ensures that if either VCCAor VCCBis less than 100 mV, the output port (B) enters a high-impedance state. The AEC-Q100 qualified 2N7001T-Q1 device is a single-bit buffered voltage signal converter that uses two separate configurable power-supply rails to up or down translate a unidirectional signal. The device is operational with both VCCAand VCCBsupplies down to 1.65 V and up to 3.60 V. VCCAdefines the input threshold voltage on the A input. VCCBdefines the output drive voltage on the B output. This device is fully specified for partial-power-down applications using the Ioffcurrent. The Ioffprotection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down. The VCCisolation feature ensures that if either VCCAor VCCBis less than 100 mV, the output port (B) enters a high-impedance state.