CY29FCT520T Series

8-Bit Multi-Level Pipeline Register

Catalog

8-Bit Multi-Level Pipeline Register

Part	Output Type	Package / Case [custom]	Package / Case	Package / Case [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Number of Bits per Element	Number of Elements	Mounting Type	Logic Type	Supplier Device Package	Function	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case	Package / Case
Texas Instruments CY29FCT520CTSOCT	Tri-State	7.5 mm	24-SOIC	0.295 in	85 °C	-40 °C	8	1	Surface Mount	Pipeline Register	24-SOIC	Universal	4.75 V	5.5 V
Texas Instruments CY29FCT520BTSOCT	Tri-State	7.5 mm	24-SOIC	0.295 in	85 °C	-40 °C	8	1	Surface Mount	Pipeline Register	24-SOIC	Universal	4.75 V	5.5 V
Texas Instruments CY29FCT520ATPCG4	Tri-State		24-DIP		85 °C	-40 °C	8	1	Through Hole	Pipeline Register	24-PDIP	Universal	4.75 V	5.5 V	0.3 in	7.62 mm
Texas Instruments CY29FCT520CTSOCE4	Tri-State	7.5 mm	24-SOIC	0.295 in	85 °C	-40 °C	8	1	Surface Mount	Pipeline Register	24-SOIC	Universal	4.75 V	5.5 V
Texas Instruments CY29FCT520ATPC	Tri-State		24-DIP		85 °C	-40 °C	8	1	Through Hole	Pipeline Register	24-PDIP	Universal	4.75 V	5.5 V	0.3 in	7.62 mm
Texas Instruments CY29FCT520CTSOCG4	Tri-State	7.5 mm	24-SOIC	0.295 in	85 °C	-40 °C	8	1	Surface Mount	Pipeline Register	24-SOIC	Universal	4.75 V	5.5 V
Texas Instruments CY29FCT520BTSOC	Tri-State	7.5 mm	24-SOIC	0.295 in	85 °C	-40 °C	8	1	Surface Mount	Pipeline Register	24-SOIC	Universal	4.75 V	5.5 V
Texas Instruments CY29FCT520ATSOC	Tri-State	7.5 mm	24-SOIC	0.295 in	85 °C	-40 °C	8	1	Surface Mount	Pipeline Register	24-SOIC	Universal	4.75 V	5.5 V
Texas Instruments CY29FCT520CTSOC	Tri-State	7.5 mm	24-SOIC	0.295 in	85 °C	-40 °C	8	1	Surface Mount	Pipeline Register	24-SOIC	Universal	4.75 V	5.5 V

Catalog

8-Bit Multi-Level Pipeline Register

Key Features

• Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29520Reduced VOH(Typically = 3.3 V) Version of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall TimesFully Compatible With TTL Input and Output Logic LevelsESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Single- and Dual-Pipeline Operation ModesMultiplexed Data Inputs and OutputsCY29FCT520T64-mA Output Sink Current32-mA Output Source CurrentCY29FCT520ATDMB, CY29FCT520BTDMB32-mA Output Sink Current12-mA Output Source Current3-State OutputsFunction, Pinout, and Drive Compatible With FCT, F Logic, and AM29520Reduced VOH(Typically = 3.3 V) Version of Equivalent FCT FunctionsEdge-Rate Control Circuitry for Significantly Improved Noise CharacteristicsIoffSupports Partial-Power-Down Mode OperationMatched Rise and Fall TimesFully Compatible With TTL Input and Output Logic LevelsESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Single- and Dual-Pipeline Operation ModesMultiplexed Data Inputs and OutputsCY29FCT520T64-mA Output Sink Current32-mA Output Source CurrentCY29FCT520ATDMB, CY29FCT520BTDMB32-mA Output Sink Current12-mA Output Source Current3-State Outputs

Description

The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0and S1). The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode. In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0and S1). The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode. In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.