| Development Boards, Kits, Programmers | 4 | Active | |
| Evaluation and Demonstration Boards and Kits | 3 | Active | |
LMH1980Auto-detecting SD/HD/PC video sync separator | Evaluation and Demonstration Boards and Kits | 3 | Active | The LMH1980 is an auto-detecting SD/HD/PC video sync separator ideal for use in a wide range of video applications, such as automotive LCD monitors, video capture & editing devices, surveillance & security equipment, and machine vision and inspection systems.
The LMH1980 accepts an analog video input signal with either bi-level or tri-level sync and automatically detects the video format, eliminating the need for external RSETresistor adjustment required by other sync separators (e.g.: LM1881). The outputs provide timing signals in CMOS logic, including Composite, Horizontal, and Vertical Syncs, Burst/Back Porch Timing, and Odd/Even Field outputs. TheHDflag output (pin 5) provides a logic low signal only when a valid HD video input with tri-level sync is detected. TheHDflag can be used to disable an external switch-controlled SD chroma filter when HD video is detected, or enable it when SD video is detected. For non-standard video with bi-level sync and without vertical serration pulses, a default vertical sync pulse will be output and no horizontal sync pulses will be output during the vertical sync interval.
The LMH1980 is available in a space-saving 10-lead Mini-SO Package (VSSOP) and operates over a temperature range of −40°C to +85°C.
The LMH1980 is an auto-detecting SD/HD/PC video sync separator ideal for use in a wide range of video applications, such as automotive LCD monitors, video capture & editing devices, surveillance & security equipment, and machine vision and inspection systems.
The LMH1980 accepts an analog video input signal with either bi-level or tri-level sync and automatically detects the video format, eliminating the need for external RSETresistor adjustment required by other sync separators (e.g.: LM1881). The outputs provide timing signals in CMOS logic, including Composite, Horizontal, and Vertical Syncs, Burst/Back Porch Timing, and Odd/Even Field outputs. TheHDflag output (pin 5) provides a logic low signal only when a valid HD video input with tri-level sync is detected. TheHDflag can be used to disable an external switch-controlled SD chroma filter when HD video is detected, or enable it when SD video is detected. For non-standard video with bi-level sync and without vertical serration pulses, a default vertical sync pulse will be output and no horizontal sync pulses will be output during the vertical sync interval.
The LMH1980 is available in a space-saving 10-lead Mini-SO Package (VSSOP) and operates over a temperature range of −40°C to +85°C. |
| Video Processing | 2 | Active | |
LMH1982Multi-rate video clock generator with Genlock | Development Boards, Kits, Programmers | 2 | Active | The LMH1982 device is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), high-definition (HD), and standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems.
The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the device's phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference ports. The input reference can have analog timing from Texas Instrument's LMH1981 multi-format video sync separator or digital timing from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device can default to free run operation where the output timing accuracy will be determined by the external bias on the free run control voltage input.
The LMH1982 can replace discrete PLLs and field-programmable gate array (FPGA) PLLs with multiple voltage controlled crystal oscillators (VCXOs). Only one 27.0000 MHz VCXO and loop filter are externally required for genlock mode. The external loop filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize jitter transfer. HD clock output jitter as low as 40 ps peak-to-peak can help designers using FPGA SerDes meet stringent SDI output jitter specifications.
The LMH1982 is offered in a space-saving 5 mm × 5 mm 32-pin WQFN package and provides low total power consumption of about 250 mW (typical).
The LMH1982 device is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), high-definition (HD), and standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems.
The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the device's phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference ports. The input reference can have analog timing from Texas Instrument's LMH1981 multi-format video sync separator or digital timing from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device can default to free run operation where the output timing accuracy will be determined by the external bias on the free run control voltage input.
The LMH1982 can replace discrete PLLs and field-programmable gate array (FPGA) PLLs with multiple voltage controlled crystal oscillators (VCXOs). Only one 27.0000 MHz VCXO and loop filter are externally required for genlock mode. The external loop filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize jitter transfer. HD clock output jitter as low as 40 ps peak-to-peak can help designers using FPGA SerDes meet stringent SDI output jitter specifications.
The LMH1982 is offered in a space-saving 5 mm × 5 mm 32-pin WQFN package and provides low total power consumption of about 250 mW (typical). |
LMH19833G/HD/SD video clock generator with audio clock | Linear | 3 | Active | The LMH1983 is a highly-integrated programmable audio/video (A/V) clock generator intended for broadcast and professional applications. It can replace multiple PLLs and VCXOs used in applications supporting SMPTE serial digital video (SDI) and digital audio AES3/EBU standards. It offers low-jitter reference clocks for any SDI transmitter to meet stringent output jitter specifications without additional clock cleaning circuits.
The LMH1983 features automatic input format detection, simple programming of multiple A/V output formats, genlock or digital free-run modes, and override programmability of various automatic functions. The recognized input formats include HVF syncs for the major video standards, 27 MHz, 10 MHz, and 32/44.1/48/96 kHz audio word clocks.
The dual-stage PLL architecture integrates four PLLs with three on-chip VCOs. The first stage (PLL1) uses an external low-noise 27 MHz VCXO with narrow loop bandwidth to provide a clean reference clock for the next stage. The second stage (PLL2, 3, 4) consists of three parallel VCO PLLs for simultaneous generation of the major digital A/V clock fundamental rates, including 148.5 MHz, 148.5/1.001 MHz, and 98.304 MHz (4 × 24.576 MHz). Each PLL can generate a clock and a timing pulse to indicate top of frame (TOF).
When locked to reference, an internal 10-bit ADC will track the loop filter control voltage. When a loss of reference (LOR) occurs, the LMH1983 can be programmed to hold the control voltage to maintain output accuracy within ±0.5 ppm (typical) of the previous reference. The LMH1983 can be configured to re-synchronize to a previous reference with glitch-less operation.
The LMH1983 is a highly-integrated programmable audio/video (A/V) clock generator intended for broadcast and professional applications. It can replace multiple PLLs and VCXOs used in applications supporting SMPTE serial digital video (SDI) and digital audio AES3/EBU standards. It offers low-jitter reference clocks for any SDI transmitter to meet stringent output jitter specifications without additional clock cleaning circuits.
The LMH1983 features automatic input format detection, simple programming of multiple A/V output formats, genlock or digital free-run modes, and override programmability of various automatic functions. The recognized input formats include HVF syncs for the major video standards, 27 MHz, 10 MHz, and 32/44.1/48/96 kHz audio word clocks.
The dual-stage PLL architecture integrates four PLLs with three on-chip VCOs. The first stage (PLL1) uses an external low-noise 27 MHz VCXO with narrow loop bandwidth to provide a clean reference clock for the next stage. The second stage (PLL2, 3, 4) consists of three parallel VCO PLLs for simultaneous generation of the major digital A/V clock fundamental rates, including 148.5 MHz, 148.5/1.001 MHz, and 98.304 MHz (4 × 24.576 MHz). Each PLL can generate a clock and a timing pulse to indicate top of frame (TOF).
When locked to reference, an internal 10-bit ADC will track the loop filter control voltage. When a loss of reference (LOR) occurs, the LMH1983 can be programmed to hold the control voltage to maintain output accuracy within ±0.5 ppm (typical) of the previous reference. The LMH1983 can be configured to re-synchronize to a previous reference with glitch-less operation. |
| RF Evaluation and Development Kits, Boards | 4 | Active | |
LMH21108 GHz Logarithmic RMS Power Detector With 45 dB Dynamic Range | Development Boards, Kits, Programmers | 4 | Active | The LMH2110 is a 45-dB Logarithmic RMS power detector particularly suited for accurate power measurement of modulated RF signals that exhibit large peak-to-average ratios; that is, large variations of the signal envelope. Such signals are encountered in W-CDMA and LTE cell phones. The RMS measurement topology inherently ensures a modulation insensitive measurement.
The device has an RF frequency range from 50 MHz to 8 GHz. It provides an accurate, temperature and supply insensitive output voltage that relates linearly to the RF input power in dBm. The LMH2110 device has excellent conformance to a logarithmic response, enabling easy integration by using slope and intercept only, reducing calibration effort significantly. The device operates with a single supply from 2.7 V to 5 V. The LMH2110 has an RF power detection range from –40 dBm to 5 dBm and is ideally suited for use in combination with a directional coupler. Alternatively, a resistive divider can be used.
The device is active for EN = High; otherwise, it is in a low power-consumption shutdown mode. To save power and prevent discharge of an external filter capacitance, the output (OUT) is high-impedance during shutdown.
The LMH2110 is a 45-dB Logarithmic RMS power detector particularly suited for accurate power measurement of modulated RF signals that exhibit large peak-to-average ratios; that is, large variations of the signal envelope. Such signals are encountered in W-CDMA and LTE cell phones. The RMS measurement topology inherently ensures a modulation insensitive measurement.
The device has an RF frequency range from 50 MHz to 8 GHz. It provides an accurate, temperature and supply insensitive output voltage that relates linearly to the RF input power in dBm. The LMH2110 device has excellent conformance to a logarithmic response, enabling easy integration by using slope and intercept only, reducing calibration effort significantly. The device operates with a single supply from 2.7 V to 5 V. The LMH2110 has an RF power detection range from –40 dBm to 5 dBm and is ideally suited for use in combination with a directional coupler. Alternatively, a resistive divider can be used.
The device is active for EN = High; otherwise, it is in a low power-consumption shutdown mode. To save power and prevent discharge of an external filter capacitance, the output (OUT) is high-impedance during shutdown. |
| RF and Wireless | 2 | Active | |
| RF Detectors | 2 | Active | |
