65MLVD205100-Mbps full-duplex M-LVDS transceiver | Drivers, Receivers, Transceivers | 4 | Active | This series of SN65MLVD20x devices are low-voltage differential line drivers and receivers complying with the proposed multipoint low-voltage differential signaling (M-LVDS) standard (TIA/EIA–899). These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. Driver output current has been increased to support doubly-terminated, 50-load multipoint applications. Driver output slew rates are optimized for signaling rates up to 100 Mbps.
Types 1 and 2 receivers are available. Both types of receivers operate over a common-mode voltage range of –1 V to 3.4 V to provide increased noise immunity in harsh electrical environments. Type-1 receivers have their differential input voltage thresholds near zero volts (±50 mV), and include 25 mV of hysteresis to prevent output oscillations in the presence of noise. Type-2 receivers include an offset threshold to detect open-circuit, idle-bus, and other fault conditions, and provide a known output state under these conditions.
The intended application of these devices is in half-duplex or multipoint baseband data transmission over controlled impedance media of approximately 100-characteristic impedance. The transmission media may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application-specific characteristics).
These devices are characterized for operation from –40°C to 85°C.
This series of SN65MLVD20x devices are low-voltage differential line drivers and receivers complying with the proposed multipoint low-voltage differential signaling (M-LVDS) standard (TIA/EIA–899). These circuits are similar to their TIA/EIA-644 standard compliant LVDS counterparts, with added features to address multipoint applications. Driver output current has been increased to support doubly-terminated, 50-load multipoint applications. Driver output slew rates are optimized for signaling rates up to 100 Mbps.
Types 1 and 2 receivers are available. Both types of receivers operate over a common-mode voltage range of –1 V to 3.4 V to provide increased noise immunity in harsh electrical environments. Type-1 receivers have their differential input voltage thresholds near zero volts (±50 mV), and include 25 mV of hysteresis to prevent output oscillations in the presence of noise. Type-2 receivers include an offset threshold to detect open-circuit, idle-bus, and other fault conditions, and provide a known output state under these conditions.
The intended application of these devices is in half-duplex or multipoint baseband data transmission over controlled impedance media of approximately 100-characteristic impedance. The transmission media may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application-specific characteristics).
These devices are characterized for operation from –40°C to 85°C. |
| Drivers, Receivers, Transceivers | 5 | Active | The SN65MLVD206B device is a multipoint low-voltage differential signaling (M-LVDS) line driver and receiver which is optimized to operate at signaling rates up to 200 Mbps. This device has a robust 3.3-V driver and receiver in the standard SOIC footprint for demanding industrial applications. The bus pins are robust to ESD events, with high levels of protection to human-body model and IEC contact discharge specifications.
The device combines a differential driver and a differential receiver (transceiver), which operates from a single 3.3-V supply. The transceiver is optimized to operate at signaling rates up to 200 Mbps.
The SN65MLVD206B has enhancements over similar devices. Improved features include a controlled slew rate on the driver output to help minimize reflections from unterminated stubs, resulting in better signal integrity. The same footprint definition was maintained, allowing for an easy drop-in replacement for a system performance upgrade. The devices are characterized for operation from –40°C to 85°C.
The SN65MLVD206B M-LVDS transceiver is part of the TI extensiveM-LVDS portfolio.
The SN65MLVD206B device is a multipoint low-voltage differential signaling (M-LVDS) line driver and receiver which is optimized to operate at signaling rates up to 200 Mbps. This device has a robust 3.3-V driver and receiver in the standard SOIC footprint for demanding industrial applications. The bus pins are robust to ESD events, with high levels of protection to human-body model and IEC contact discharge specifications.
The device combines a differential driver and a differential receiver (transceiver), which operates from a single 3.3-V supply. The transceiver is optimized to operate at signaling rates up to 200 Mbps.
The SN65MLVD206B has enhancements over similar devices. Improved features include a controlled slew rate on the driver output to help minimize reflections from unterminated stubs, resulting in better signal integrity. The same footprint definition was maintained, allowing for an easy drop-in replacement for a system performance upgrade. The devices are characterized for operation from –40°C to 85°C.
The SN65MLVD206B M-LVDS transceiver is part of the TI extensiveM-LVDS portfolio. |
| Drivers, Receivers, Transceivers | 2 | Active | |
| DSP (Digital Signal Processors) | 13 | Active | |
| Embedded | 4 | Active | |
66AK2G12High performance multicore DSP+Arm - 1x Arm A15 cores, 1x C66x DSP core | DSP (Digital Signal Processors) | 7 | Active | 66AK2G1x is a family of heterogeneous multicore System-on-Chip (SoC) devices based on TI’s field-proven Keystone II (KS2) architecture. These devices address applications that require both DSP and Arm performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems (HLOS) support.
Similar to existing KS2-based SoC devices, the 66AK2G1x enables both the DSP and Arm cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or Arm-centric system designs can be achieved.
The 66AK2G1x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G1x parts satisfy a wide range of industrial requirements.
Accompanied by the new Processor SDK, the 66AK2G1x development platform enables unprecedented ease-of-use with main line open source Linux, Code Composer Studio™ (CCS) - Integrated Development Environment (IDE), a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and Arm, such as system trace and seamless integration of the Arm CoreSight components.
Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.
66AK2G1x is a family of heterogeneous multicore System-on-Chip (SoC) devices based on TI’s field-proven Keystone II (KS2) architecture. These devices address applications that require both DSP and Arm performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems (HLOS) support.
Similar to existing KS2-based SoC devices, the 66AK2G1x enables both the DSP and Arm cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or Arm-centric system designs can be achieved.
The 66AK2G1x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G1x parts satisfy a wide range of industrial requirements.
Accompanied by the new Processor SDK, the 66AK2G1x development platform enables unprecedented ease-of-use with main line open source Linux, Code Composer Studio™ (CCS) - Integrated Development Environment (IDE), a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and Arm, such as system trace and seamless integration of the Arm CoreSight components.
Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative. |
| Embedded | 11 | Active | |
| DSP (Digital Signal Processors) | 5 | Active | |
| Embedded | 3 | Active | |
| DSP (Digital Signal Processors) | 4 | Active | |
