65LVDT41Enhanced product Memorystick™ interconnect extender chipset | Interface | 3 | Active | The SN65LVDTxx devices are multi-channel LVDS transceivers that operate using LVDS line drivers and receivers. The SN65LVDTxx devices support signaling rates of at least 250 Mbps, and the devices operate from a single supply (typically at 3.3 V) in a 20-pin TSSOP package designed for easy PCB layout.
The SN65LVDT14 and SN65LVDT41 provide general-purpose, asymmetric, bidirectional communication with the added benefit of high noise immunity, low electromagnetic interference (EMI), and increased cable length through the use of LVDS lines. The SN65LVDT14 and SN65LVDT41 are primarily used for SPI over LVDS applications.
The SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. The SN65LVDT14 can be used to extend asymmetric, bidirectional interfaces such as SPI over long distances, and should be located at the SPI slave.
The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package. The SN65LVDT41 can be used to extend asymmetric, bidirectional interfaces such as SPI over long distances, and should be located at the SPI master.
The SN65LVDTxx devices are multi-channel LVDS transceivers that operate using LVDS line drivers and receivers. The SN65LVDTxx devices support signaling rates of at least 250 Mbps, and the devices operate from a single supply (typically at 3.3 V) in a 20-pin TSSOP package designed for easy PCB layout.
The SN65LVDT14 and SN65LVDT41 provide general-purpose, asymmetric, bidirectional communication with the added benefit of high noise immunity, low electromagnetic interference (EMI), and increased cable length through the use of LVDS lines. The SN65LVDT14 and SN65LVDT41 are primarily used for SPI over LVDS applications.
The SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. The SN65LVDT14 can be used to extend asymmetric, bidirectional interfaces such as SPI over long distances, and should be located at the SPI slave.
The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package. The SN65LVDT41 can be used to extend asymmetric, bidirectional interfaces such as SPI over long distances, and should be located at the SPI master. |
| Integrated Circuits (ICs) | 3 | Active | This family of differential line receivers offers improved performance and features that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard, providing a better overall solution for the cabled environment. This generation of products is an extension to TI's overall product portfolio and is not necessarily a replacement for older LVDS receivers.
Improved features include an input common-mode voltage range 2 V wider than the minimum required by the standard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between a driver and receiver. TI has additionally introduced an even wider input common-mode voltage range of -4 to 5 V in their SN65LVDS/T33 and SN65LVDS/T34.
Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range.
The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The non-terminated SN65LVDS series is also available for multidrop or other termination circuits.
The receivers can withstand ±15-kV human-body model (HBM) and ±600 V-machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for wired-OR bus signaling.
The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B, SN65LVDT3486B, SN65LVDS9637B, and SN65LVDT9637B are characterized for operation from -40°C to 85°C.
This family of differential line receivers offers improved performance and features that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard, providing a better overall solution for the cabled environment. This generation of products is an extension to TI's overall product portfolio and is not necessarily a replacement for older LVDS receivers.
Improved features include an input common-mode voltage range 2 V wider than the minimum required by the standard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between a driver and receiver. TI has additionally introduced an even wider input common-mode voltage range of -4 to 5 V in their SN65LVDS/T33 and SN65LVDS/T34.
Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range.
The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The non-terminated SN65LVDS series is also available for multidrop or other termination circuits.
The receivers can withstand ±15-kV human-body model (HBM) and ±600 V-machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for wired-OR bus signaling.
The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B, SN65LVDT3486B, SN65LVDS9637B, and SN65LVDT9637B are characterized for operation from -40°C to 85°C. |
| Clock Buffers, Drivers | 4 | Active | The SN65LVEL11 is a fully differential 1:2 ECL fanout buffer. The device includes circuitry to maintain a known logic level when inputs are in open condition. The SN65LVEL11 is functionally equivalent to SN65EL11 with improved performance. The SN65LVEL11 is housed in an industry standard SOIC-8 package and is also available in the TSSOP-8 package option.
The SN65LVEL11 is a fully differential 1:2 ECL fanout buffer. The device includes circuitry to maintain a known logic level when inputs are in open condition. The SN65LVEL11 is functionally equivalent to SN65EL11 with improved performance. The SN65LVEL11 is housed in an industry standard SOIC-8 package and is also available in the TSSOP-8 package option. |
| Integrated Circuits (ICs) | 2 | Active | |
| Interface | 1 | Active | |
65LVP192.5-V/3.3-V oscillator gain stage/buffer with enable | Interface | 1 | Active | These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
These four devices are high frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx18) and fully differential inputs on the SN65LVx19.
The SN65LVx18 provides the user a Gain Control (GC) for controlling theQoutput from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, theQoutput defaults to 575 mV.) TheQon the SN65LVx19 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C. |
65LVP204-Gbps PECL to LVPECL repeater | Signal Buffers, Repeaters, Splitters | 1 | Active | The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.
The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input toENenables the outputs. A high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential transmission lines with nominally 100-characteristic impedance.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.
The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input toENenables the outputs. A high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential transmission lines with nominally 100-characteristic impedance.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCCfor use in receiving single-ended PECL input signals. When not used, VBBshould be unconnected or open.
All devices are characterized for operation from -40°C to 85°C. |
65LVPE5021st generation dual channel USB 3.0 redriver with rotated package | Signal Buffers, Repeaters, Splitters | 7 | NRND | The SN65LVPE502 is a dual channel, single lane USB 3.0 redriver and signal conditioner supporting data rates of 5.0Gbps. The device complies with USB 3.0 spec revision 1.0, supporting electrical idle condition and low frequency periodic signals (LFPS) for USB 3.0 power management modes.
Programmable EQ, De-Emphasis and Amplitude Swing
The SN65LVPE502 is designed to minimize signal degradation effects such as crosstalk and inter-symbol interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel offers selectable equalization settings that can be programmed to match loss in the channel. The differential outputs provide selectable de-emphasis to compensate for the anticipated distortion USB 3.0 signal will experience. Level of de-emphasis will depend on the length of interconnect and its characteristics. The SN65LVPE502 provides a unique way to tailor output de-emphasis on a per channel basis with use of DE and OS pins. All Rx and Tx equalization settings supported by the device are programmed by six 3-state pins as shown in .
Low Power Modes
The device supports three low power modes as described below.
Initiated anytime EN_RXD undergoes a high to low transition or when device powers up with EN_RXD set low. In sleep mode both input and output terminations are held at HiZ and device ceases operation to conserve power. Sleep mode max power consumption is 1mW, entry time is 2µs, device exits sleep mode to Rx.Detect mode after EN_RXD is driven to VCC, exit time is 100µs max.
Anytime SN65LVPE502 detects a break in link (i.e., when upstream device is disconnected) or after powerup fails to find a remote device, SN65LVPE502 goes to Rx Detect mode and conserves power by shutting down majority of the internal circuitry. In this mode, input termination for both channels are driven to Hi-Z. In Rx Detect mode device power is <10mW(TYP) or less than 5% of its normal operating power This feature is useful in saving system power in mobile applications like notebook PC where battery life is critical.
Anytime an upstream device gets reconnected the redriver automatically senses the connection and goes to normal operating mode. This operation requires no setting to the device.
With the help of internal timers the device tracks when link enters USB 3.0 low power modes U2 and U3, in these modes link is in electrical idle state. SN65LVPE502 will selectively turn-off internal circuitry to save on power. Typical power saving is about 75% lower than normal operating mode. The device will automatically revert to active mode when signaling activity (LFPS) is detected.
Receiver Detection
RX.Detect cycle is performed by first setting Rx termination for each channel to Hi-Z, device then starts sensing for receiver termination that may be attached at the other end of each TX.
If receiver is detected on both channel:
If no receiver is detected on one or both channels:
USB Compliance Mode
The device enters USB compliance mode when both EN_RXD and CM pins are set H. This mode is used to test the transmitter for compliance to voltage and timing specifications per USB 3.0 compliance specs. In this mode each channel will maintain its low-impedance termination RDC-RX, while auto Rx detect operation in the device is disabled.
Electrical Idle Support
The electrical idle support is needed for low frequency periodic signaling (LFPS) used in USB 3.0 side band communication. A link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common mode voltage. SN65LVPE502 detects an electrical idle state when RX± voltage at the device pin falls below VRX_IDLE_DIFFppmin. After detection of an idle state in a given channel the device asserts electrical idle state in its corresponding TX. When RX± voltage exceeds VRX_IDLE_DIFFppmax normal operation is restored and output start passing input signal. The electrical idle exit and entry time is specified at ≤6 ns.
The SN65LVPE502 is a dual channel, single lane USB 3.0 redriver and signal conditioner supporting data rates of 5.0Gbps. The device complies with USB 3.0 spec revision 1.0, supporting electrical idle condition and low frequency periodic signals (LFPS) for USB 3.0 power management modes.
Programmable EQ, De-Emphasis and Amplitude Swing
The SN65LVPE502 is designed to minimize signal degradation effects such as crosstalk and inter-symbol interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel offers selectable equalization settings that can be programmed to match loss in the channel. The differential outputs provide selectable de-emphasis to compensate for the anticipated distortion USB 3.0 signal will experience. Level of de-emphasis will depend on the length of interconnect and its characteristics. The SN65LVPE502 provides a unique way to tailor output de-emphasis on a per channel basis with use of DE and OS pins. All Rx and Tx equalization settings supported by the device are programmed by six 3-state pins as shown in .
Low Power Modes
The device supports three low power modes as described below.
Initiated anytime EN_RXD undergoes a high to low transition or when device powers up with EN_RXD set low. In sleep mode both input and output terminations are held at HiZ and device ceases operation to conserve power. Sleep mode max power consumption is 1mW, entry time is 2µs, device exits sleep mode to Rx.Detect mode after EN_RXD is driven to VCC, exit time is 100µs max.
Anytime SN65LVPE502 detects a break in link (i.e., when upstream device is disconnected) or after powerup fails to find a remote device, SN65LVPE502 goes to Rx Detect mode and conserves power by shutting down majority of the internal circuitry. In this mode, input termination for both channels are driven to Hi-Z. In Rx Detect mode device power is <10mW(TYP) or less than 5% of its normal operating power This feature is useful in saving system power in mobile applications like notebook PC where battery life is critical.
Anytime an upstream device gets reconnected the redriver automatically senses the connection and goes to normal operating mode. This operation requires no setting to the device.
With the help of internal timers the device tracks when link enters USB 3.0 low power modes U2 and U3, in these modes link is in electrical idle state. SN65LVPE502 will selectively turn-off internal circuitry to save on power. Typical power saving is about 75% lower than normal operating mode. The device will automatically revert to active mode when signaling activity (LFPS) is detected.
Receiver Detection
RX.Detect cycle is performed by first setting Rx termination for each channel to Hi-Z, device then starts sensing for receiver termination that may be attached at the other end of each TX.
If receiver is detected on both channel:
If no receiver is detected on one or both channels:
USB Compliance Mode
The device enters USB compliance mode when both EN_RXD and CM pins are set H. This mode is used to test the transmitter for compliance to voltage and timing specifications per USB 3.0 compliance specs. In this mode each channel will maintain its low-impedance termination RDC-RX, while auto Rx detect operation in the device is disabled.
Electrical Idle Support
The electrical idle support is needed for low frequency periodic signaling (LFPS) used in USB 3.0 side band communication. A link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common mode voltage. SN65LVPE502 detects an electrical idle state when RX± voltage at the device pin falls below VRX_IDLE_DIFFppmin. After detection of an idle state in a given channel the device asserts electrical idle state in its corresponding TX. When RX± voltage exceeds VRX_IDLE_DIFFppmax normal operation is restored and output start passing input signal. The electrical idle exit and entry time is specified at ≤6 ns. |
| Integrated Circuits (ICs) | 1 | Active | |
65LVPE5122nd generation dual channel USB 3.0 redriver | Signal Buffers, Repeaters, Splitters | 2 | NRND | The SN65LVPE512 device is a dual-channel, single-lane USB 3.0 redriver and signal conditioner supporting data rates of 5 Gbps. The device complies with USB 3.0 spec revision 1.0, supporting electrical idle condition and low frequency periodic signals (LFPS) for USB 3.0 power management modes.
The SN65LVPE512 device is a dual-channel, single-lane USB 3.0 redriver and signal conditioner supporting data rates of 5 Gbps. The device complies with USB 3.0 spec revision 1.0, supporting electrical idle condition and low frequency periodic signals (LFPS) for USB 3.0 power management modes. |
