Texas Instruments

The DAC3482 is a very low power, high dynamic range, dual-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25GSPS. The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90dB of stop-band attenuation simplify the data interface and reconstruction filters. A complex mixer allows flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. Digital data is input to the device through a flexible LVDS data bus with on-chip termination. Data can be input either word-wide or byte-wide. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices. The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a small 88 pin 9 x 9mm WQFN-MR package or 196-ball 12 x12mm NFBGA package. Low power, small size, superior crosstalk, high dynamic range, and features of the DAC3482 make it an ideal fit for today’s communication systems. The DAC3482 is a very low power, high dynamic range, dual-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25GSPS. The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90dB of stop-band attenuation simplify the data interface and reconstruction filters. A complex mixer allows flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. Digital data is input to the device through a flexible LVDS data bus with on-chip termination. Data can be input either word-wide or byte-wide. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices. The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a small 88 pin 9 x 9mm WQFN-MR package or 196-ball 12 x12mm NFBGA package. Low power, small size, superior crosstalk, high dynamic range, and features of the DAC3482 make it an ideal fit for today’s communication systems.

The DAC3484 is a very low power, high dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25 GSPS. The device includes features that simplify the design of complex transmit architectures: 2× to 16× digital interpolation filters with over 90dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase and group delay between channels in direct up-conversion applications. Digital data is input to the device through a 16-bit LVDS data bus with on-chip termination. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices. The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a very-small 88-pin 9x9mm WQFN package or 196-ball 12×12mm NFBGA package. Very low power, small size, superior crosstalk, high dynamic range and features of the DAC3484 are an ideal fit for systems with multiple transmit channels. The DAC3484 is a very low power, high dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25 GSPS. The device includes features that simplify the design of complex transmit architectures: 2× to 16× digital interpolation filters with over 90dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase and group delay between channels in direct up-conversion applications. Digital data is input to the device through a 16-bit LVDS data bus with on-chip termination. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices. The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a very-small 88-pin 9x9mm WQFN package or 196-ball 12×12mm NFBGA package. Very low power, small size, superior crosstalk, high dynamic range and features of the DAC3484 are an ideal fit for systems with multiple transmit channels.

The DAC34H84 is a very low power, high dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25 GSPS. The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase and group delay between channels in direct up-conversion applications. Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip termination. The wide bus allows the processing of very high bandwidth signals. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices. The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a 196-ball, 12x12mm, 0.8mm pitch BGA package. The DAC34H84 very low power, high bandwidth support, superior crosstalk, high dynamic range and features are an ideal fit for next generation communication systems. The DAC34H84 is a very low power, high dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25 GSPS. The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase and group delay between channels in direct up-conversion applications. Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip termination. The wide bus allows the processing of very high bandwidth signals. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices. The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a 196-ball, 12x12mm, 0.8mm pitch BGA package. The DAC34H84 very low power, high bandwidth support, superior crosstalk, high dynamic range and features are an ideal fit for next generation communication systems.

The DAC34SH84 is a very low-power, high-dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.5 GSPS. The device includes features that simplify the design of complex transmit architectures: 2× to 16× digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement. A high-performance low-jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital quadrature modulator correction (QMC) enables complete IQ compensation for gain, offset and phase between channels in direct upconversion applications. Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip termination. The wide bus allows the processing of high-bandwidth signals. The device includes a FIFO, data pattern checker, and parity test to ease the input interface. The interface also allows full synchronization of multiple devices. The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a 196-ball, 12-mm × 12-mm, 0.8-mm pitch NFBGA package. The DAC34SH84 low-power, high-bandwidth support, superior crosstalk, high dynamic range, and features are an ideal fit for next-generation communication systems. The DAC34SH84 is a very low-power, high-dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.5 GSPS. The device includes features that simplify the design of complex transmit architectures: 2× to 16× digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement. A high-performance low-jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital quadrature modulator correction (QMC) enables complete IQ compensation for gain, offset and phase between channels in direct upconversion applications. Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip termination. The wide bus allows the processing of high-bandwidth signals. The device includes a FIFO, data pattern checker, and parity test to ease the input interface. The interface also allows full synchronization of multiple devices. The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a 196-ball, 12-mm × 12-mm, 0.8-mm pitch NFBGA package. The DAC34SH84 low-power, high-bandwidth support, superior crosstalk, high dynamic range, and features are an ideal fit for next-generation communication systems.

The pin-compatible DAC37J82/DAC38J82 family is a very low power, 16-bit, dual-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface. The maximum input data rate is 1.23 GSPS. Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices. The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement. A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected. DAC37J82/DAC38J82 family provides four analog outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC outputs via the output multiplexer. The pin-compatible DAC37J82/DAC38J82 family is a very low power, 16-bit, dual-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface. The maximum input data rate is 1.23 GSPS. Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices. The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement. A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected. DAC37J82/DAC38J82 family provides four analog outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC outputs via the output multiplexer.

The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface. Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices. The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement. A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected. The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface. Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices. The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement. A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.

The pin-compatible DAC37J82/DAC38J82 family is a very low power, 16-bit, dual-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface. The maximum input data rate is 1.23 GSPS. Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices. The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement. A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected. DAC37J82/DAC38J82 family provides four analog outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC outputs via the output multiplexer. The pin-compatible DAC37J82/DAC38J82 family is a very low power, 16-bit, dual-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface. The maximum input data rate is 1.23 GSPS. Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices. The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement. A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected. DAC37J82/DAC38J82 family provides four analog outputs, and the data from the internal two digital paths can be routed to any two out of these four DAC outputs via the output multiplexer.