DAC37J84 Series

Quad-Channel, 16-Bit, 1.6-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC)

Catalog

Quad-Channel, 16-Bit, 1.6-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC)

Part	Number of Bits	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Settling Time	Package / Case	Number of D/A Converters	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Output Type	Reference Type	Architecture	INL/DNL (LSB)	Supplier Device Package	Mounting Type	Data Interface	Differential Output
Texas Instruments DAC37J84IAAV	16	85 °C	-40 °C	3.15 V	3.45 V	10 ns	144-FBGA FCBGA	4	0.95 V	0.85 V	Current - Unbuffered	External Internal	Current Source	±4 ±6	144-FCBGA (10x10)	Surface Mount	JESD204B
Texas Instruments DAC37J84IAAVR	16	85 °C	-40 °C	3.15 V	3.45 V	10 ns	144-FBGA FCBGA	4	0.95 V	0.85 V	Current - Unbuffered	External Internal	Current Source	±4 ±6	144-FCBGA (10x10)	Surface Mount	JESD204B

Catalog

Quad-Channel, 16-Bit, 1.6-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC)

Key Features

• Resolution: 16-BitMaximum Sample Rate:DAC37J84: 1.6 GSPSDAC38J84: 2.5 GSPSMaximum Input Data Rate: 1.23GSPSJESD204B Interface8 JESD204B Serial Input Lanes12.5 Gbps Maximum Bit Rate per LaneSubclass 1 Multi-DAC SynchronizationOn-Chip Very Low Jitter PLLSelectable 1x -16x InterpolationIndependent Complex Mixers with 48-bit NCO/or ±n×Fs/8Wideband Digital Quadrature Modulator CorrectionSinx/x Correction FiltersFractional Sample Group Delay CorrectionMulti-Band Mode: Digital Summation of IndependentComplex Signals3/4-Wire Serial Control Bus (SPI):1.5V – 1.8VIntegrated Temperature SensorJTAG Boundary ScanTerminal-Compatible with Dual-Channel DAC37J82/DAC38J82 FamilyPower Dissipation: 1.8W at 2.5GSPSPackage: 10x10mm, 144-Ball Flip-Chip BGAResolution: 16-BitMaximum Sample Rate:DAC37J84: 1.6 GSPSDAC38J84: 2.5 GSPSMaximum Input Data Rate: 1.23GSPSJESD204B Interface8 JESD204B Serial Input Lanes12.5 Gbps Maximum Bit Rate per LaneSubclass 1 Multi-DAC SynchronizationOn-Chip Very Low Jitter PLLSelectable 1x -16x InterpolationIndependent Complex Mixers with 48-bit NCO/or ±n×Fs/8Wideband Digital Quadrature Modulator CorrectionSinx/x Correction FiltersFractional Sample Group Delay CorrectionMulti-Band Mode: Digital Summation of IndependentComplex Signals3/4-Wire Serial Control Bus (SPI):1.5V – 1.8VIntegrated Temperature SensorJTAG Boundary ScanTerminal-Compatible with Dual-Channel DAC37J82/DAC38J82 FamilyPower Dissipation: 1.8W at 2.5GSPSPackage: 10x10mm, 144-Ball Flip-Chip BGA

Description

The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface. Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices. The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement. A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected. The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface. Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices. The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement. A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.