| Development Boards, Kits, Programmers | 4 | Obsolete | |
| Development Boards, Kits, Programmers | 3 | Obsolete | |
CLV4052Automotive, 5V 4:1 two-channel analog multiplexer | Analog Switches, Multiplexers, Demultiplexers | 1 | Obsolete | These dual 4-channel CMOS analog multiplexers and demultiplexers are designed for 1.0V to 5.5V VCC operation.
The SN7LV4052A-Q1 devices handle both analog and digital signals. Each channel permits signals with amplitudes up to 5.5V (peak).
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.
These dual 4-channel CMOS analog multiplexers and demultiplexers are designed for 1.0V to 5.5V VCC operation.
The SN7LV4052A-Q1 devices handle both analog and digital signals. Each channel permits signals with amplitudes up to 5.5V (peak).
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. |
CLVC138Automotive Catalog 3-Line To 8-Line decoder/Demultiplexer | Logic | 1 | Active | The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.
The device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.
The device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. |
CLVC157Automotive quadruple 2-line-to-1-line data selector/multiplexer | Signal Switches, Multiplexers, Decoders | 1 | Active | The SN74LVC157A quadruple 2-line to 1-line data selector/multiplexer is designed for 2.7V to 3.6V VCC operation.
The SN74LVC157A quadruple 2-line to 1-line data selector/multiplexer is designed for 2.7V to 3.6V VCC operation. |
| Logic | 1 | Obsolete | |
CLVC244Automotive 8-ch, 1.65-V to 3.6-V buffers with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 2 | Active | These octal bus buffers are designed for 1.65V to 3.6V VCC operation. The SN74LVC244A-Q1 devices are designed for asynchronous communication between data buses.
These octal bus buffers are designed for 1.65V to 3.6V VCC operation. The SN74LVC244A-Q1 devices are designed for asynchronous communication between data buses. |
| Integrated Circuits (ICs) | 1 | Obsolete | |
CLVC574Automotive Catalog Octal Edge-Triggered D-Type Flip-Flop With 3-State Outputs | Logic | 2 | Active | The SN74LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OEdoes not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of thIs device as a translator in a mixed 3.3-V/5-V system environment.
The SN74LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OEdoes not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of thIs device as a translator in a mixed 3.3-V/5-V system environment. |
| Integrated Circuits (ICs) | 1 | Obsolete | |
