| Clock Generators, PLLs, Frequency Synthesizers | 1 | Obsolete | |
CDC421A100100-MHz fully integrated fixed frequency low-jitter crystal oscillator clock generator | Clock Generators, PLLs, Frequency Synthesizers | 1 | Active | The CDC421Axxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz to 2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for a phase-locked loop (PLL)-based frequency synthesizer. The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL).
The device operates in 3.3-V supply environment and is characterized for operation from -40°C to +85°C. The CDC421Axxx is available in a QFN-24 4-mm × 4-mm package.
The CDC421Axxx differs from the CDC421xxx in the following ways:
The CDC421Axxx has an improved startup circuit to enable correct operation for all power-supply ramp times.
The CDC421Axxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz to 2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for a phase-locked loop (PLL)-based frequency synthesizer. The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL).
The device operates in 3.3-V supply environment and is characterized for operation from -40°C to +85°C. The CDC421Axxx is available in a QFN-24 4-mm × 4-mm package.
The CDC421Axxx differs from the CDC421xxx in the following ways:
The CDC421Axxx has an improved startup circuit to enable correct operation for all power-supply ramp times. |
CDC421A106106.25-MHz fully integrated fixed frequency low-jitter crystal oscillator clock generator | Clock/Timing | 2 | Active | The CDC421Axxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz to 2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for a phase-locked loop (PLL)-based frequency synthesizer. The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL).
The device operates in 3.3-V supply environment and is characterized for operation from -40°C to +85°C. The CDC421Axxx is available in a QFN-24 4-mm × 4-mm package.
The CDC421Axxx differs from the CDC421xxx in the following ways:
The CDC421Axxx has an improved startup circuit to enable correct operation for all power-supply ramp times.
The CDC421Axxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz to 2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for a phase-locked loop (PLL)-based frequency synthesizer. The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL).
The device operates in 3.3-V supply environment and is characterized for operation from -40°C to +85°C. The CDC421Axxx is available in a QFN-24 4-mm × 4-mm package.
The CDC421Axxx differs from the CDC421xxx in the following ways:
The CDC421Axxx has an improved startup circuit to enable correct operation for all power-supply ramp times. |
CDC421A156156.25-MHz fully integrated fixed frequency low-jitter crystal oscillator clock generator | Clock/Timing | 1 | Active | The CDC421Axxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz to 2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for a phase-locked loop (PLL)-based frequency synthesizer. The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL).
The device operates in 3.3-V supply environment and is characterized for operation from -40°C to +85°C. The CDC421Axxx is available in a QFN-24 4-mm × 4-mm package.
The CDC421Axxx differs from the CDC421xxx in the following ways:
The CDC421Axxx has an improved startup circuit to enable correct operation for all power-supply ramp times.
The CDC421Axxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz to 2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for a phase-locked loop (PLL)-based frequency synthesizer. The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL).
The device operates in 3.3-V supply environment and is characterized for operation from -40°C to +85°C. The CDC421Axxx is available in a QFN-24 4-mm × 4-mm package.
The CDC421Axxx differs from the CDC421xxx in the following ways:
The CDC421Axxx has an improved startup circuit to enable correct operation for all power-supply ramp times. |
CDC421A250250-MHz fully integrated fixed frequency low-jitter crystal oscillator clock generator | Clock Generators, PLLs, Frequency Synthesizers | 1 | Active | The CDC421Axxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz to 2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for a phase-locked loop (PLL)-based frequency synthesizer. The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL).
The device operates in 3.3-V supply environment and is characterized for operation from -40°C to +85°C. The CDC421Axxx is available in a QFN-24 4-mm × 4-mm package.
The CDC421Axxx differs from the CDC421xxx in the following ways:
The CDC421Axxx has an improved startup circuit to enable correct operation for all power-supply ramp times.
The CDC421Axxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz to 2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for a phase-locked loop (PLL)-based frequency synthesizer. The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL).
The device operates in 3.3-V supply environment and is characterized for operation from -40°C to +85°C. The CDC421Axxx is available in a QFN-24 4-mm × 4-mm package.
The CDC421Axxx differs from the CDC421xxx in the following ways:
The CDC421Axxx has an improved startup circuit to enable correct operation for all power-supply ramp times. |
CDC421A312312.5-MHz fully integrated fixed frequency low-jitter crystal oscillator clock generator | Clock Generators, PLLs, Frequency Synthesizers | 2 | Active | The CDC421Axxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz to 2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for a phase-locked loop (PLL)-based frequency synthesizer. The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL).
The device operates in 3.3-V supply environment and is characterized for operation from -40°C to +85°C. The CDC421Axxx is available in a QFN-24 4-mm × 4-mm package.
The CDC421Axxx differs from the CDC421xxx in the following ways:
The CDC421Axxx has an improved startup circuit to enable correct operation for all power-supply ramp times.
The CDC421Axxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz to 2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for a phase-locked loop (PLL)-based frequency synthesizer. The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL).
The device operates in 3.3-V supply environment and is characterized for operation from -40°C to +85°C. The CDC421Axxx is available in a QFN-24 4-mm × 4-mm package.
The CDC421Axxx differs from the CDC421xxx in the following ways:
The CDC421Axxx has an improved startup circuit to enable correct operation for all power-supply ramp times. |
CDC5093.3-V phase lock loop clock driver | Clock/Timing | 2 | Active | The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCCand is designed to drive up to five clock loads per output.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCCto ground.
The CDC509 is characterized for operation from 0°C to 70°C.
The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCCand is designed to drive up to five clock loads per output.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCCto ground.
The CDC509 is characterized for operation from 0°C to 70°C. |
| Clock Generators, PLLs, Frequency Synthesizers | 3 | Active | |
CDC536100-MHz, 3.3-V PLL clock driver with 1/2x, 1x and 2x frequency options | Clock/Timing | 3 | Active | The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCCand is designed to drive a 50-W transmission line.
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock.
Output-enable (OE)\ is provided for output control. When OE\ is high, the outputs are in the high-impedance state. When OE\ is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon enable of all outputs via OE\.
The CDC536 is characterized for operation from 0°C to 70°C.
The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCCand is designed to drive a 50-W transmission line.
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock.
Output-enable (OE)\ is provided for output control. When OE\ is high, the outputs are in the high-impedance state. When OE\ is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon enable of all outputs via OE\.
The CDC536 is characterized for operation from 0°C to 70°C. |
CDC5801ALow-jitter clock multiplier & divider with programmable delay & phase alignment | Clock/Timing | 3 | Active | The CDC5801A device provides clock multiplication and division from a single-ended reference clock (REFCLK) to a differential output pair (CLKOUT/CLKOUTB). The multiply and divide terminals (MULT/DIV0:1) provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 12.5 MHz to 500 MHz with a clock input reference (REFCLK) ranging from 19 MHz to 125 MHz.
The implemented phase aligner provides the possibility to phase align (zero delay) between CLKOUT/CLKOUTB and REFCLK or any other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG terminals.
The phase aligner also allows the user to delay or advance the CLKOUT/CLKOUTB with steps of 2.6 mUI (unit interval). For every rising edge on the DLYCTRL terminal, the output clocks are delayed by 2.6-mUI step size as long as there is low on the LEADLAG terminal. Similarly, for every rising edge on the DLYCTRL terminal, the output clocks are advanced by 2.6-mUI step size as long as there is high on the LEADLAG terminal. The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions. As the phase between REFCLK and CLKOUT/CLKOUTB is random after power up, the application may implement a self calibration routine at power up to produce a certain phase start position, before programming a fixed delay with the clock on the DLYCTRL terminal.
Depending on the selection of the mode terminals (P0:2), the device behaves as a multiplier (by 4, 6, or 8) with the phase aligner bypassed or as a multiplier or divider with programmable delay and phase aligner functionality. Through the select terminals (P0:2) user can also bypass the phase aligner and the PLL (test mode) and output the REFCLK directly on the CLKOUT/CLKOUTB terminals. Through P0:2 terminals the outputs could be in a high impedance state. This device has another unique capability to be able to function with a wide band of voltages on the REFCLK terminal by varying the voltage on the VDDREF terminal.
The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions.
The CDC5801A device is characterized for operation over free-air temperatures of –40°C to 85°C.
The CDC5801A device provides clock multiplication and division from a single-ended reference clock (REFCLK) to a differential output pair (CLKOUT/CLKOUTB). The multiply and divide terminals (MULT/DIV0:1) provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies ranging from 12.5 MHz to 500 MHz with a clock input reference (REFCLK) ranging from 19 MHz to 125 MHz.
The implemented phase aligner provides the possibility to phase align (zero delay) between CLKOUT/CLKOUTB and REFCLK or any other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG terminals.
The phase aligner also allows the user to delay or advance the CLKOUT/CLKOUTB with steps of 2.6 mUI (unit interval). For every rising edge on the DLYCTRL terminal, the output clocks are delayed by 2.6-mUI step size as long as there is low on the LEADLAG terminal. Similarly, for every rising edge on the DLYCTRL terminal, the output clocks are advanced by 2.6-mUI step size as long as there is high on the LEADLAG terminal. The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions. As the phase between REFCLK and CLKOUT/CLKOUTB is random after power up, the application may implement a self calibration routine at power up to produce a certain phase start position, before programming a fixed delay with the clock on the DLYCTRL terminal.
Depending on the selection of the mode terminals (P0:2), the device behaves as a multiplier (by 4, 6, or 8) with the phase aligner bypassed or as a multiplier or divider with programmable delay and phase aligner functionality. Through the select terminals (P0:2) user can also bypass the phase aligner and the PLL (test mode) and output the REFCLK directly on the CLKOUT/CLKOUTB terminals. Through P0:2 terminals the outputs could be in a high impedance state. This device has another unique capability to be able to function with a wide band of voltages on the REFCLK terminal by varying the voltage on the VDDREF terminal.
The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions.
The CDC5801A device is characterized for operation over free-air temperatures of –40°C to 85°C. |
