CD74HC4094High speed CMOS Logic 8-stage shift-and-store bus register with 3-stage outputs | Integrated Circuits (ICs) | 10 | Active | High speed CMOS Logic 8-stage shift-and-store bus register with 3-stage outputs |
CD74HC42High Speed CMOS Logic 1-of-10 BCD to Decimal Decoder | Signal Switches, Multiplexers, Decoders | 5 | Active | The ’HC42 and CD74HCT42 BCD-to-Decimal Decoders utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL decoders with the low power consumption of standard CMOS integrated circuits. These devices have the capability of driving 10 LSTLL loads and are compatible with the standard LS logic family. One of ten outputs (low on select) is selected in accordance with the BCD input. Non-valid BCD inputs result in none of the outputs being selected (all outputs are high).
The ’HC42 and CD74HCT42 BCD-to-Decimal Decoders utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL decoders with the low power consumption of standard CMOS integrated circuits. These devices have the capability of driving 10 LSTLL loads and are compatible with the standard LS logic family. One of ten outputs (low on select) is selected in accordance with the BCD input. Non-valid BCD inputs result in none of the outputs being selected (all outputs are high). |
CD74HC423High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Reset | Logic | 4 | Active | The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are dual monostable multivibrators with resets. They are all retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse; whereas the 423 types do not have this feature. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of Rx and CXprovides a wide range of output pulse widths from the Q and Q\ terminals. Pulse triggering on the A\ and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses.
Once triggered, the output pulse width may be extended by retriggering inputs A\ and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing edge triggering (A)\ and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used each input on the unused device (A\, B, and R\) must be terminated high or low.
The minimum value of external resistance, Rx is typically 5k. The minimum value external capacitance, CX, is 0pF. The calculation for the pulse width is tW= 0.45 RXCXat VCC= 5V.
The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are dual monostable multivibrators with resets. They are all retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse; whereas the 423 types do not have this feature. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of Rx and CXprovides a wide range of output pulse widths from the Q and Q\ terminals. Pulse triggering on the A\ and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses.
Once triggered, the output pulse width may be extended by retriggering inputs A\ and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing edge triggering (A)\ and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used each input on the unused device (A\, B, and R\) must be terminated high or low.
The minimum value of external resistance, Rx is typically 5k. The minimum value external capacitance, CX, is 0pF. The calculation for the pulse width is tW= 0.45 RXCXat VCC= 5V. |
CD74HC43165-V, 1:1 (SPST), 4-channel analog switch with level translation | Integrated Circuits (ICs) | 13 | Active | The ’HC4316 and CD74HCT4316 contain four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.
In addition these devices contain logic-level translation circuits that provide for analog signal switching of voltages between ±5V via 5V logic. Each switch is turned on by a high-level voltage on its select input (S) when the common Enable (E) is Low. A High E disables all switches. The digital inputs can swing between VCC and GND; the analog inputs/outputs can swing between VCC as a positive limit and VEE as a negative limit. Voltage ranges are shown in Figure 13-1 and Figure 13-2.
The ’HC4316 and CD74HCT4316 contain four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.
In addition these devices contain logic-level translation circuits that provide for analog signal switching of voltages between ±5V via 5V logic. Each switch is turned on by a high-level voltage on its select input (S) when the common Enable (E) is Low. A High E disables all switches. The digital inputs can swing between VCC and GND; the analog inputs/outputs can swing between VCC as a positive limit and VEE as a negative limit. Voltage ranges are shown in Figure 13-1 and Figure 13-2. |
CD74HC43515-V, 8:1, 1-channel analog mutliplexer with latch | Analog Switches, Multiplexers, Demultiplexers | 4 | Active | The ’HC4351, CD74HCT4351, and CD74HC4352 are digitally controlled analog switches which utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.
These analog multiplexers/demultiplexers are, in essence, the HC/HCT4015 and HC4052 preceded by address latches that are controlled by an active low Latch Enable input (LE\). Two Enable inputs, one active low (E1\), and the other active high (E2) are provided allowing enabling with either input voltage level.
The ’HC4351, CD74HCT4351, and CD74HC4352 are digitally controlled analog switches which utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.
These analog multiplexers/demultiplexers are, in essence, the HC/HCT4015 and HC4052 preceded by address latches that are controlled by an active low Latch Enable input (LE\). Two Enable inputs, one active low (E1\), and the other active high (E2) are provided allowing enabling with either input voltage level. |
CD74HC43525-V, 4:1 differential, 1-channel analog mutliplexer with latch | Integrated Circuits (ICs) | 1 | Obsolete | The ’HC4351, CD74HCT4351, and CD74HC4352 are digitally controlled analog switches which utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.
These analog multiplexers/demultiplexers are, in essence, the HC/HCT4015 and HC4052 preceded by address latches that are controlled by an active low Latch Enable input (LE\). Two Enable inputs, one active low (E1\), and the other active high (E2) are provided allowing enabling with either input voltage level.
The ’HC4351, CD74HCT4351, and CD74HC4352 are digitally controlled analog switches which utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.
These analog multiplexers/demultiplexers are, in essence, the HC/HCT4015 and HC4052 preceded by address latches that are controlled by an active low Latch Enable input (LE\). Two Enable inputs, one active low (E1\), and the other active high (E2) are provided allowing enabling with either input voltage level. |
CD74HC4511High Speed CMOS Logic BCD-to-7 Segment Latch/Decoder/Driver | Integrated Circuits (ICs) | 10 | Active | High Speed CMOS Logic BCD-to-7 Segment Latch/Decoder/Driver |
CD74HC4514High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer with Input Latches | Logic | 4 | Active | The CD54HC4514, CD74HC4514, and CD74HC4515 are high-speed silicon gate devices consisting of a 4-bit strobed latch and a 4-to-16 line decoder. The selected output is enabled by a low on the enable input (E\). A high on E\ inhibits selection of any output. Demultiplexing is accomplished by using the E\ input as the data input and the select inputs (A0-A3) as addresses. This E\ input also serves as a chip select when these devices are cascaded.
When Latch Enable (LE\) is high the output follows changes in the inputs (see truth table). When LE is low the output is isolated from changes in the input and remains at the level (high for the 4514, low for the 4515) it had before the latches were enabled. These devices, enhanced versions of the equivalent CMOS types, can drive 10 LSTTL loads.
The CD54HC4514, CD74HC4514, and CD74HC4515 are high-speed silicon gate devices consisting of a 4-bit strobed latch and a 4-to-16 line decoder. The selected output is enabled by a low on the enable input (E\). A high on E\ inhibits selection of any output. Demultiplexing is accomplished by using the E\ input as the data input and the select inputs (A0-A3) as addresses. This E\ input also serves as a chip select when these devices are cascaded.
When Latch Enable (LE\) is high the output follows changes in the inputs (see truth table). When LE is low the output is isolated from changes in the input and remains at the level (high for the 4514, low for the 4515) it had before the latches were enabled. These devices, enhanced versions of the equivalent CMOS types, can drive 10 LSTTL loads. |
CD74HC4518High Speed CMOS Logic Dual BCD Up-Counter | Counters, Dividers | 1 | Active | The CD74HC4518 is a dual BCD up-counter. The ’HC4520 and CD74HCT4520 are dual binary up-counters. Each device consists of two independent internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negative-going transition of CLOCK. The counters are cleared by high levels on the MASTER RESET lines. The counter can be cascaded in the ripple mode by connecting Q3to the ENABLE input of the subsequent counter while the CLOCK input of the latter is held low.
The CD74HC4518 is a dual BCD up-counter. The ’HC4520 and CD74HCT4520 are dual binary up-counters. Each device consists of two independent internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negative-going transition of CLOCK. The counters are cleared by high levels on the MASTER RESET lines. The counter can be cascaded in the ripple mode by connecting Q3to the ENABLE input of the subsequent counter while the CLOCK input of the latter is held low. |
CD74HC4520High Speed CMOS Logic Dual Binary Up-Counters | Logic | 3 | Active | The CD74HC4518 is a dual BCD up-counter. The ’HC4520 and CD74HCT4520 are dual binary up-counters. Each device consists of two independent internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negative-going transition of CLOCK. The counters are cleared by high levels on the MASTER RESET lines. The counter can be cascaded in the ripple mode by connecting Q3to the ENABLE input of the subsequent counter while the CLOCK input of the latter is held low.
The CD74HC4518 is a dual BCD up-counter. The ’HC4520 and CD74HCT4520 are dual binary up-counters. Each device consists of two independent internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negative-going transition of CLOCK. The counters are cleared by high levels on the MASTER RESET lines. The counter can be cascaded in the ripple mode by connecting Q3to the ENABLE input of the subsequent counter while the CLOCK input of the latter is held low. |
