TSB81BA3Enhanced product IEEE 1394b 3-port cable transceiver/arbiter | Interface | 7 | Obsolete | The TSB81BA3 provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB81BA3 is designed to interface with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It may also be connected cable port to cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2.
The TSB81BA3 is powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-CORE and DVDD-CORE terminals to the requirements in the recommended operating conditions. The PLLVDD-CORE terminals must be separated from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1 µF and smaller decoupling capacitors, and the DVDD-CORE terminals separately decoupled with a 1 µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE may be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by a filter network to keep noise from the PLLVDD-CORE supply.
The TSB81BA3 requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two devices and is used for resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE 1394a-2000 standard. A 98.304-MHz clock signal is supplied to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE P1394b standard. The power down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.
Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are latched internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbits/s (referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream.
The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the P1394b standard.
The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When any of the three ports is connected to a 1394a-2000 compliant device, the cable interface on that port operates in the 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b compliant node, the cable interface on that port operates per the P1394b standard at S400B or S800 speed. The TSB81BA3 automatically determines the correct cable interface connection method for the bilingual ports.
NOTE:The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal selects the PHY-link interface mode of operation and affects the arbitration modes on the cable. When the BMODE terminal is deasserted, BOSS arbitration is disabled.
During packet reception the serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected and active cable ports.
Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration when connected to a 1394a-2000 compliant device. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage.
When connected to a 1394a-2000 compliant node, the TSB81BA3 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF.
The line drivers in the TSB81BA3, are designed to work with external 112-and 270 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents.
When the power supply of the TSB81BA3 is off while the twisted-pair cables are connected, the TSB81BA3 transmitter and receiver circuitry present a high-impedance signal to the cable that does not load the device at the other end of the cable.
When the TSB81BA3 is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the port must be forced to the 1394a-only mode (Data-Strobe-only mode), then the TPB+ and TPB- terminals can be tied together and then pulled to ground; or the TPB+ and TPB- terminals can be connected to the suggested normal termination network. The TPA+ and TPA- terminals of an unused port can be left unconnected. The TPBIAS terminal can be connected to a 1-µF capacitor to ground or left unconnected.
To operate a port as a 1394b bilingual port, the force data-strobe-only terminal for the port (DS0, DS1, or DS2) needs to be pulled to ground through a 1-kresistor. The only time the port must be forced to the data-strobe-only mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode is provided to ensure that 1394b signalling is never sent across a 1394a cable.
The TESTM, TESTW, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM and TESTW terminals must be connected to VDDthrough a 1-kresistor.
Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They may be pulled high through a 1-kresistor or hardwired low as a function of the equipment design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for power from the cable or the ability to supply power to the cable). The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the TSB81BA3, this bit may only be set by a write to the PHY register set. If a node desires to be a contender for IRM or BM, then the node software must set this bit in the PHY register set.
The LPS (link power status) terminal works with the LKON/DS2 terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit).
The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB81BA3 detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB81BA3 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB81BA3 issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible).
The PHY uses the LKON/DS2 terminal to notify the LLC to power up and become active. When activated, the output LKON/DS2 signal is a square wave. The PHY activates the LKON/DS2 output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the LKON/DS2 output when the LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the LKON/DS2 output when a bus reset occurs, unless a PHY interrupt condition exists which would otherwise cause LKON/DS2 to be active. If the PHY is power cycled and the power class is 0 through 4, then the PHY asserts LKON/DS2 for approximately 167 µs or until both the LPS is active and the LCtrl bit is 1.
The TSB81BA3 provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB81BA3 is designed to interface with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It may also be connected cable port to cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2.
The TSB81BA3 is powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-CORE and DVDD-CORE terminals to the requirements in the recommended operating conditions. The PLLVDD-CORE terminals must be separated from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1 µF and smaller decoupling capacitors, and the DVDD-CORE terminals separately decoupled with a 1 µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE may be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by a filter network to keep noise from the PLLVDD-CORE supply.
The TSB81BA3 requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two devices and is used for resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE 1394a-2000 standard. A 98.304-MHz clock signal is supplied to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE P1394b standard. The power down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.
Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are latched internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbits/s (referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream.
The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the P1394b standard.
The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When any of the three ports is connected to a 1394a-2000 compliant device, the cable interface on that port operates in the 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b compliant node, the cable interface on that port operates per the P1394b standard at S400B or S800 speed. The TSB81BA3 automatically determines the correct cable interface connection method for the bilingual ports.
NOTE:The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal selects the PHY-link interface mode of operation and affects the arbitration modes on the cable. When the BMODE terminal is deasserted, BOSS arbitration is disabled.
During packet reception the serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected and active cable ports.
Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration when connected to a 1394a-2000 compliant device. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage.
When connected to a 1394a-2000 compliant node, the TSB81BA3 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF.
The line drivers in the TSB81BA3, are designed to work with external 112-and 270 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents.
When the power supply of the TSB81BA3 is off while the twisted-pair cables are connected, the TSB81BA3 transmitter and receiver circuitry present a high-impedance signal to the cable that does not load the device at the other end of the cable.
When the TSB81BA3 is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the port must be forced to the 1394a-only mode (Data-Strobe-only mode), then the TPB+ and TPB- terminals can be tied together and then pulled to ground; or the TPB+ and TPB- terminals can be connected to the suggested normal termination network. The TPA+ and TPA- terminals of an unused port can be left unconnected. The TPBIAS terminal can be connected to a 1-µF capacitor to ground or left unconnected.
To operate a port as a 1394b bilingual port, the force data-strobe-only terminal for the port (DS0, DS1, or DS2) needs to be pulled to ground through a 1-kresistor. The only time the port must be forced to the data-strobe-only mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode is provided to ensure that 1394b signalling is never sent across a 1394a cable.
The TESTM, TESTW, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM and TESTW terminals must be connected to VDDthrough a 1-kresistor.
Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They may be pulled high through a 1-kresistor or hardwired low as a function of the equipment design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for power from the cable or the ability to supply power to the cable). The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the TSB81BA3, this bit may only be set by a write to the PHY register set. If a node desires to be a contender for IRM or BM, then the node software must set this bit in the PHY register set.
The LPS (link power status) terminal works with the LKON/DS2 terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit).
The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB81BA3 detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB81BA3 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB81BA3 issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible).
The PHY uses the LKON/DS2 terminal to notify the LLC to power up and become active. When activated, the output LKON/DS2 signal is a square wave. The PHY activates the LKON/DS2 output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the LKON/DS2 output when the LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the LKON/DS2 output when a bus reset occurs, unless a PHY interrupt condition exists which would otherwise cause LKON/DS2 to be active. If the PHY is power cycled and the power class is 0 through 4, then the PHY asserts LKON/DS2 for approximately 167 µs or until both the LPS is active and the LCtrl bit is 1. |
TSB82AA2High performance 1394b 3.3-V OHCI 1.1+ compliant link layer controller | Controllers | 4 | Active | The TSB82AA2 OHCI-Lynx is a discrete 1394b link-layer device, which has been designed to meet the demanding requirements of today’s 1394 bus designs. The TSB82AA2 device is capable of exceptional 800M bits/s performance; thus, providing the throughput and bandwidth to move data efficiently and quickly between the PCI and 1394 buses. The TSB82AA2 device also provides outstanding ultra-low power operation and intelligent power management capabilities. The device provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s serial bus data rates.
The TSB82AA2 improved throughput and increased bandwidth make it ideal for today’s high-end PCs and open the door for the development of S800 RAID- and SAN-based peripherals.
The TSB82AA2 OHCI-Lynx operates as the interface between a 33-MHz/64-bit or 33-MHz/32-bit PCI local bus and a compatible 1394b PHY-layer device (such as the TSB81BA3 device) that is capable of supporting serial data rates at 98.304M, 196.608M, 393.216M, or 786.432M bits/s (referred to as S100, S200, S400, or S800 speeds, respectively). When acting as a PCI bus master, the TSB82AA2 device is capable ofmultiple cacheline bursts of data, which can transfer at 264M bytes/s for 64-bit transfers or 132M bytes/s for 32-bit transfers after connecting to the memory controller.
Due to the high throughput potential of the TSB82AA2 device, it possible to encounter large PCI and legacy 1394 bus latencies, which can cause the 1394 data to be overrun. To overcome this potential problem, the TSB82AA2 implements deep transmit and receive FIFOs to buffer the 1394 data, thus preventing possible problems due to bus latency. This also ensures that the device can transmit and receive sustained maximum size isochronous or asynchronous data payloads at S800.
The TSB82AA2 device implements other performance enhancements to improve overall performance of the device, such as: a highly tuned physical data path for enhanced SBP-2 performance, physical post writing buffers, multiple isochronous contexts, and advanced internal arbitration.
The TSB82AA2 device also implements hardware enhancements to better support digital video (DV) and MPEG data stream reception and transmission. These enhancements are enabled through the isochronous receive digital video enhancements register at TI extension offset A80h. These enhancements include automatic time stamp insertion for transmitted DV and MPEG-formatted streams and common isochronous packet (CIP) header stripping for received DV streams.
The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data contexts are implemented as hardware support for the synchronization timestamp for both DV and audio/video CIP formats. The TSB82AA2 device supports modification of the synchronization timestamp field to ensure that the value inserted via software is not stale—that is, less than the current cycle timer when the packet is transmitted.
The TSB82AA2 performance and enhanced throughput make it an excellent choice for today’s 1394 PC market; however, the portable, mobile, and even today’s desktop PCs power management schemes continue to require devices to use less and less power, and Texas Instrument’s 1394 OHCI-Lynx product line has continued to raise the bar by providing the lowest power 1394 link-layers in the industry. The TSB82AA2 device represents the next evolution of Texas Instruments commitment to meet the challenge of power-sensitive applications. The TSB82AA2 device has ultra-low operational power requirements and intelligent power management capabilities that allow it to autonomously conserve power based on the device usage.
One of the key elements for reducing the TSB82AA2 operational power requirements is Texas Instrument’s advanced CMOS process and the implementation of an internal 1.8-V core, which is supplied by an improved integrated 3.3-V to 1.8-V voltage regulator. The TSB82AA2 device implements a next generation voltage regulator which is more efficient than its predecessors, thus providing an overall reduction in the device’s operational power requirements especially when operating in D3coldusing auxiliary power. In fact, the TSB82AA2 device fully supports D0, D1, D2, and D3hot/coldpower states as specified in thePC 2001 Design Guiderequirements and thePCI Power Management Specification. PME wake event support is subject to operating system support and implementation.
As required by the1394 Open Host Controller Interface Specification(OHCI) and IEEE Std 1394a--2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles as specified by thePCI Local Bus Specification, and provides plug-and-play (PnP) compatibility. Furthermore, the TSB82AA2 device is fully compliant with the latestPCI Local Bus Specification,PCI Bus Power Management Interface Specification, IEEE Draft Std 1394b, IEEE Std 1394a--2000, and1394 Open Host Controller Interface Specification.
The TSB82AA2 OHCI-Lynx is a discrete 1394b link-layer device, which has been designed to meet the demanding requirements of today’s 1394 bus designs. The TSB82AA2 device is capable of exceptional 800M bits/s performance; thus, providing the throughput and bandwidth to move data efficiently and quickly between the PCI and 1394 buses. The TSB82AA2 device also provides outstanding ultra-low power operation and intelligent power management capabilities. The device provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s serial bus data rates.
The TSB82AA2 improved throughput and increased bandwidth make it ideal for today’s high-end PCs and open the door for the development of S800 RAID- and SAN-based peripherals.
The TSB82AA2 OHCI-Lynx operates as the interface between a 33-MHz/64-bit or 33-MHz/32-bit PCI local bus and a compatible 1394b PHY-layer device (such as the TSB81BA3 device) that is capable of supporting serial data rates at 98.304M, 196.608M, 393.216M, or 786.432M bits/s (referred to as S100, S200, S400, or S800 speeds, respectively). When acting as a PCI bus master, the TSB82AA2 device is capable ofmultiple cacheline bursts of data, which can transfer at 264M bytes/s for 64-bit transfers or 132M bytes/s for 32-bit transfers after connecting to the memory controller.
Due to the high throughput potential of the TSB82AA2 device, it possible to encounter large PCI and legacy 1394 bus latencies, which can cause the 1394 data to be overrun. To overcome this potential problem, the TSB82AA2 implements deep transmit and receive FIFOs to buffer the 1394 data, thus preventing possible problems due to bus latency. This also ensures that the device can transmit and receive sustained maximum size isochronous or asynchronous data payloads at S800.
The TSB82AA2 device implements other performance enhancements to improve overall performance of the device, such as: a highly tuned physical data path for enhanced SBP-2 performance, physical post writing buffers, multiple isochronous contexts, and advanced internal arbitration.
The TSB82AA2 device also implements hardware enhancements to better support digital video (DV) and MPEG data stream reception and transmission. These enhancements are enabled through the isochronous receive digital video enhancements register at TI extension offset A80h. These enhancements include automatic time stamp insertion for transmitted DV and MPEG-formatted streams and common isochronous packet (CIP) header stripping for received DV streams.
The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data contexts are implemented as hardware support for the synchronization timestamp for both DV and audio/video CIP formats. The TSB82AA2 device supports modification of the synchronization timestamp field to ensure that the value inserted via software is not stale—that is, less than the current cycle timer when the packet is transmitted.
The TSB82AA2 performance and enhanced throughput make it an excellent choice for today’s 1394 PC market; however, the portable, mobile, and even today’s desktop PCs power management schemes continue to require devices to use less and less power, and Texas Instrument’s 1394 OHCI-Lynx product line has continued to raise the bar by providing the lowest power 1394 link-layers in the industry. The TSB82AA2 device represents the next evolution of Texas Instruments commitment to meet the challenge of power-sensitive applications. The TSB82AA2 device has ultra-low operational power requirements and intelligent power management capabilities that allow it to autonomously conserve power based on the device usage.
One of the key elements for reducing the TSB82AA2 operational power requirements is Texas Instrument’s advanced CMOS process and the implementation of an internal 1.8-V core, which is supplied by an improved integrated 3.3-V to 1.8-V voltage regulator. The TSB82AA2 device implements a next generation voltage regulator which is more efficient than its predecessors, thus providing an overall reduction in the device’s operational power requirements especially when operating in D3coldusing auxiliary power. In fact, the TSB82AA2 device fully supports D0, D1, D2, and D3hot/coldpower states as specified in thePC 2001 Design Guiderequirements and thePCI Power Management Specification. PME wake event support is subject to operating system support and implementation.
As required by the1394 Open Host Controller Interface Specification(OHCI) and IEEE Std 1394a--2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles as specified by thePCI Local Bus Specification, and provides plug-and-play (PnP) compatibility. Furthermore, the TSB82AA2 device is fully compliant with the latestPCI Local Bus Specification,PCI Bus Power Management Interface Specification, IEEE Draft Std 1394b, IEEE Std 1394a--2000, and1394 Open Host Controller Interface Specification. |
