| Analog Switches - Special Purpose | 8 | Active | |
| Interface | 1 | Active | |
TS5V3305-V, 2:1 (SPDT), 4-channel video switch | Analog Switches - Special Purpose | 11 | Active | The TS5V330 video switch is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (EN) input. WhenENis low, the switch is enabled and the D port is connected to the S port. WhenENis high, the switch is disabled and the high-impedance state exists between the D and S ports. The select (IN) input controls the data path of the multiplexer/demultiplexer.
Low differential gain and phase make this switch ideal for composite and RGB video applications. This device has wide bandwidth and low crosstalk, making it suitable for high-frequency applications as well.
This device is fully specified for partial-power-down applications using Ioff. The Iofffeature ensures that damaging current will not backflow through the device when it is powered down. This switch maintains isolation during power off.
To ensure the high-impedance state during power up or power down,ENshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The TS5V330 video switch is a 4-bit 1-of-2 multiplexer/demultiplexer with a single switch-enable (EN) input. WhenENis low, the switch is enabled and the D port is connected to the S port. WhenENis high, the switch is disabled and the high-impedance state exists between the D and S ports. The select (IN) input controls the data path of the multiplexer/demultiplexer.
Low differential gain and phase make this switch ideal for composite and RGB video applications. This device has wide bandwidth and low crosstalk, making it suitable for high-frequency applications as well.
This device is fully specified for partial-power-down applications using Ioff. The Iofffeature ensures that damaging current will not backflow through the device when it is powered down. This switch maintains isolation during power off.
To ensure the high-impedance state during power up or power down,ENshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
| Interface | 2 | Active | |
| Unclassified | 8 | Obsolete | |
| Interface | 2 | Active | |
| Interface | 2 | Obsolete | |
TSB12LV26OHCI-Lynx PCI-based IEEE 1394 host controller | Integrated Circuits (ICs) | 1 | Active | The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with thePCI Local BusSpecification, PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, and1394 Open HostController Interface Specification. The chip provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, and 400M bits/s serial bus data rates.
As required by the1394 Open Host Controller Interface Specification(OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the TSB12LV26 device is compliant with thePCI Bus Power Management Interface Specification, per thePC 99 Design Guiderequirements. TSB12LV26 device supports the D0, D2, and D3 power states.
The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided to buffer 1394 data.
The TSB12LV26 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface.
An advanced CMOS process achieves low power consumption and allows the TSB12LV26 device to operate at PCI clock rates up to 33 MHz.
The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with thePCI Local BusSpecification, PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, and1394 Open HostController Interface Specification. The chip provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, and 400M bits/s serial bus data rates.
As required by the1394 Open Host Controller Interface Specification(OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the TSB12LV26 device is compliant with thePCI Bus Power Management Interface Specification, per thePC 99 Design Guiderequirements. TSB12LV26 device supports the D0, D2, and D3 power states.
The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided to buffer 1394 data.
The TSB12LV26 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface.
An advanced CMOS process achieves low power consumption and allows the TSB12LV26 device to operate at PCI clock rates up to 33 MHz. |
| Interface | 1 | NRND | |
TSB12LV32General-purpose link layer controller (GP2Lynx) | Controllers | 3 | Active | The TSB12LV32 (GP2Lynx) is a high-performance general-purpose IEEE 1394a-2000 link-layer controller (LLC) with the capability of transferring data between a host controller, the 1394 Phy-link interface, and external devices connected to the data mover port (local bus interface). The 1394 Phy-link interface provides the connection to the 1394 physical layer device and is supported by the LLC. The LLC provides the control for transmitting and receiving 1394 packet data between the microcontroller interface and the Phy-link interface via internal 2K byte FIFOs at rates up to 400 Mbit/s. The TSB12LV32 transmits and receives correctly formatted 1394 packets, generates and detects the 1394 cycle start packets, communicates transaction layer transmit requests to the Phy, and generates and inspects the 32-bit cyclic redundancy check (CRC).
The TSB12LV32 is capable of being cycle master (CM),1394 bus manager, 1394 isochronous resource manager (IRM)if additional control status registers (CSRs) are added via the external host controller, and supports reception of 1394 isochronous data on two channels and transmission of 1394 isochronous data on four channels.
The TSB12LV32 supports a direct interface to many microprocessors/microcontrollers by including programmable endian swapping. TSB12LV32 has a generic 16/8-bit host bus interface which includes support for the ColdFire™ microcontroller mode at rates up to 60 MHz. The microinterface can operate in byte or word (16 bit) accesses.
The data-mover block in GP2Lynx handles the external memory interface of large data blocks. This local bus interface can be configured to either transmit or receive data packets. The packets can be either asynchronous, isochronous, or asynchronous streaming data packets. The data-mover (DM) port can receive any type of packet, but it can only transmit one type of packet at a time: isochronous data packets, asynchronous data packets, or asynchronous stream data packets.
The internal FIFO is separated into an asynchronous transmit FIFO (ATF) and a general receive FIFO (GRF), each of 520 quadlets (2 Kbytes). Asynchronous and/or isochronous receive packets can be routed to either the DM port or the GRF via the receiver routing control logic. Asynchronous data packets or asynchronous stream data packets can be transmitted from the DM port or the internal FIFO: ATF. If there is contention the ATF has priority and is transmitted first. Isochronous packets can only be transmitted by the data-mover port.
The LLC also provides the capability to receive status information from the physical layer device and to access the physical layer control and status registers by the application software.
The TSB12LV32 (GP2Lynx) is a high-performance general-purpose IEEE 1394a-2000 link-layer controller (LLC) with the capability of transferring data between a host controller, the 1394 Phy-link interface, and external devices connected to the data mover port (local bus interface). The 1394 Phy-link interface provides the connection to the 1394 physical layer device and is supported by the LLC. The LLC provides the control for transmitting and receiving 1394 packet data between the microcontroller interface and the Phy-link interface via internal 2K byte FIFOs at rates up to 400 Mbit/s. The TSB12LV32 transmits and receives correctly formatted 1394 packets, generates and detects the 1394 cycle start packets, communicates transaction layer transmit requests to the Phy, and generates and inspects the 32-bit cyclic redundancy check (CRC).
The TSB12LV32 is capable of being cycle master (CM),1394 bus manager, 1394 isochronous resource manager (IRM)if additional control status registers (CSRs) are added via the external host controller, and supports reception of 1394 isochronous data on two channels and transmission of 1394 isochronous data on four channels.
The TSB12LV32 supports a direct interface to many microprocessors/microcontrollers by including programmable endian swapping. TSB12LV32 has a generic 16/8-bit host bus interface which includes support for the ColdFire™ microcontroller mode at rates up to 60 MHz. The microinterface can operate in byte or word (16 bit) accesses.
The data-mover block in GP2Lynx handles the external memory interface of large data blocks. This local bus interface can be configured to either transmit or receive data packets. The packets can be either asynchronous, isochronous, or asynchronous streaming data packets. The data-mover (DM) port can receive any type of packet, but it can only transmit one type of packet at a time: isochronous data packets, asynchronous data packets, or asynchronous stream data packets.
The internal FIFO is separated into an asynchronous transmit FIFO (ATF) and a general receive FIFO (GRF), each of 520 quadlets (2 Kbytes). Asynchronous and/or isochronous receive packets can be routed to either the DM port or the GRF via the receiver routing control logic. Asynchronous data packets or asynchronous stream data packets can be transmitted from the DM port or the internal FIFO: ATF. If there is contention the ATF has priority and is transmitted first. Isochronous packets can only be transmitted by the data-mover port.
The LLC also provides the capability to receive status information from the physical layer device and to access the physical layer control and status registers by the application software. |
