TSB12LV01B Series
High performance 1394 3.3-V link layer for telecom, embedded & industrial app.,32-bit i/f, 2kb FIFO
Manufacturer: Texas Instruments
Catalog
High performance 1394 3.3-V link layer for telecom, embedded & industrial app.,32-bit i/f, 2kb FIFO
Key Features
• Link CoreSupports Provision of IEEE 1394-1995 (1394) Standard for High-Performance Serial BusTransmits and Receives Correctly Formatted 1394 PacketsSupports Asynchronous and Isochronous Data TransfersPerforms Function of 1394 Cycle MasterGenerates and Checks 32-Bit CRCDetects Lost Cycle-Start MessagesContains Asynchronous, Isochronous, and General-Receive FIFOs Totaling 2K BytesPhysical-Link InterfaceCompatible With Texas Instruments Physical Layer Devices (PHYs)Supports Transfer Speeds of 100, 200, and 400 Mbits/sTiming Compliant with IEEE 1394a–2000Host Bus InterfaceProvides Chip Control With Directly Addressable RegistersIs Interrupt Driven to Minimize Host PollingHas a Generic 32-Bit Host Bus InterfaceGeneralOperates From a 3.3-V Power Supply While Maintaining 5-V Tolerant InputsManufactured With Low-Power CMOS Technology100-Pin PZT Package for 0°C to 70°C and –40°C to 85°C (I Temperature) OperationLink CoreSupports Provision of IEEE 1394-1995 (1394) Standard for High-Performance Serial BusTransmits and Receives Correctly Formatted 1394 PacketsSupports Asynchronous and Isochronous Data TransfersPerforms Function of 1394 Cycle MasterGenerates and Checks 32-Bit CRCDetects Lost Cycle-Start MessagesContains Asynchronous, Isochronous, and General-Receive FIFOs Totaling 2K BytesPhysical-Link InterfaceCompatible With Texas Instruments Physical Layer Devices (PHYs)Supports Transfer Speeds of 100, 200, and 400 Mbits/sTiming Compliant with IEEE 1394a–2000Host Bus InterfaceProvides Chip Control With Directly Addressable RegistersIs Interrupt Driven to Minimize Host PollingHas a Generic 32-Bit Host Bus InterfaceGeneralOperates From a 3.3-V Power Supply While Maintaining 5-V Tolerant InputsManufactured With Low-Power CMOS Technology100-Pin PZT Package for 0°C to 70°C and –40°C to 85°C (I Temperature) Operation
Description
AI
The TSB12LV01B is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12LV01B provides a high-performance IEEE 1394-1995 interface with the capability of transferring data between the 32-bit host bus, the 1394 PHY-link interface, and external devices connected to the local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical (PHY) layer device and is supported by the link-layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. The TSB12LV01B transmits and receives correctly-formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check (CRC). The TSB12LV01B is capable of being cycle master and supports reception of isochronous data on two channels. TSB12LV01B has a generic 32-bit host bus interface, which will connect to most 32-bit hosts. The LLC also provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software. An internal 2K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates the need for external FIFOs. Separate FIFOs can be user configured to support general 1394 receive, asynchronous transmit, and isochronous transmit transfer operations. These functions are accomplished by appropriately sizing the general receive FIFO (GRF), asynchronous transmit FIFO (ATF), and isochronous transmit FIFO (ITF).
The TSB12LV01B is a revision of the TSB12LV01A, with feature enhancements and corrections. It is pin for pin compatible with the TSB12LV01A with the restrictions noted below. It is also software compatible with the extensions noted below.
All errata items to the TSB12LV01A have been fixed, and the following feature enhancements have been made:
However, there are three restrictions that were not present in the TSB12LV01A device:
This document is not intended to serve as a tutorial on 1394; users are referred to the IEEE 1394-1995 serial bus standard for detailed information regarding the 1394 high-speed serial bus.
The TSB12LV01B is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12LV01B provides a high-performance IEEE 1394-1995 interface with the capability of transferring data between the 32-bit host bus, the 1394 PHY-link interface, and external devices connected to the local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical (PHY) layer device and is supported by the link-layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. The TSB12LV01B transmits and receives correctly-formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check (CRC). The TSB12LV01B is capable of being cycle master and supports reception of isochronous data on two channels. TSB12LV01B has a generic 32-bit host bus interface, which will connect to most 32-bit hosts. The LLC also provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software. An internal 2K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates the need for external FIFOs. Separate FIFOs can be user configured to support general 1394 receive, asynchronous transmit, and isochronous transmit transfer operations. These functions are accomplished by appropriately sizing the general receive FIFO (GRF), asynchronous transmit FIFO (ATF), and isochronous transmit FIFO (ITF).
The TSB12LV01B is a revision of the TSB12LV01A, with feature enhancements and corrections. It is pin for pin compatible with the TSB12LV01A with the restrictions noted below. It is also software compatible with the extensions noted below.
All errata items to the TSB12LV01A have been fixed, and the following feature enhancements have been made:
However, there are three restrictions that were not present in the TSB12LV01A device:
This document is not intended to serve as a tutorial on 1394; users are referred to the IEEE 1394-1995 serial bus standard for detailed information regarding the 1394 high-speed serial bus.
