Texas Instruments

The TS5USBC402 is a bidirectional low-power dual port, high-speed, USB 2.0 analog switch with integrated protection for USB Type-C™ systems. The device is configured as a dual 2:1 or 1:2 switch and is optimized for handling the USB 2.0 D+/- lines in a USB Type-C™ systems. The TS5USBC402 protection on the I/O pins can tolerate up to 20 V with automatic shutoff circuitry to protect system components behind the switch. The TS5USBC402 comes in a small 12 pin DSBGA package making it a perfect candidate for mobile and space constrained applications. The TS5USBC402 is a bidirectional low-power dual port, high-speed, USB 2.0 analog switch with integrated protection for USB Type-C™ systems. The device is configured as a dual 2:1 or 1:2 switch and is optimized for handling the USB 2.0 D+/- lines in a USB Type-C™ systems. The TS5USBC402 protection on the I/O pins can tolerate up to 20 V with automatic shutoff circuitry to protect system components behind the switch. The TS5USBC402 comes in a small 12 pin DSBGA package making it a perfect candidate for mobile and space constrained applications.

The TS5USBC41 is a bidirectional low-power dual port, high-speed, USB 2.0 analog switch with integrated protection for USB Type-C™ systems. The device is configured as a dual 2:1 or 1:2 switch. It is optimized for use with the USB 2.0 D+/- lines in a USB Type-C™ systems. The TS5USBC41 protection on the I/O pins can tolerate up to 20 V (TS5USBC410) or 24 V (TS5USBC412) with automatic shutoff circuitry to protect system components behind the switch. The TS5USBC41 comes in a small 12 pin DSBGA package making it a perfect candidate for mobile and space constrained applications. The TS5USBC41 is a bidirectional low-power dual port, high-speed, USB 2.0 analog switch with integrated protection for USB Type-C™ systems. The device is configured as a dual 2:1 or 1:2 switch. It is optimized for use with the USB 2.0 D+/- lines in a USB Type-C™ systems. The TS5USBC41 protection on the I/O pins can tolerate up to 20 V (TS5USBC410) or 24 V (TS5USBC412) with automatic shutoff circuitry to protect system components behind the switch. The TS5USBC41 comes in a small 12 pin DSBGA package making it a perfect candidate for mobile and space constrained applications.

The TS5V330C is a 4-bit 1-of-2 multiplexer/demultiplexer video switch with a single switch-enable (EN) input. The select (IN) input controls the data path of the multiplexer/demultiplexer. When EN is low, the switch is enabled and the D port is connected to the S port. WhenENis high, the switch is disabled and a high impedance state exists between the D and S ports. Low differential gain and phase makes this switch ideal for video applications. The device has a wide bandwidth and low cross talk which makes it suitable for high frequency video applications. The device can be used for RGB and composite video switching applications. This device is fully specified for partial-power-down applications using Ioff. The Iofffeature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down,ENshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The TS5V330C is a 4-bit 1-of-2 multiplexer/demultiplexer video switch with a single switch-enable (EN) input. The select (IN) input controls the data path of the multiplexer/demultiplexer. When EN is low, the switch is enabled and the D port is connected to the S port. WhenENis high, the switch is disabled and a high impedance state exists between the D and S ports. Low differential gain and phase makes this switch ideal for video applications. The device has a wide bandwidth and low cross talk which makes it suitable for high frequency video applications. The device can be used for RGB and composite video switching applications. This device is fully specified for partial-power-down applications using Ioff. The Iofffeature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down,ENshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The TS5V522C is high bandwidth analog switches offering a 2:2 dual-graphics crossover solution for VGA signal switching. The device is designed for switching between 2 VGA sources to either of the two destinations within a laptop computer. The TS5V522C integrates 5 very high-frequency 380Mhz (typ) SPDT switches for RGB signals, 2 pairs of level-translating buffer for the HSYNC and VSYNC lines, and integrated ESD protection. The 5 crossover switches can be controlled by either 5V or 3.3V TTL control signals. The TS5V522C would bypass the VGA analog signal to destination with less distortions. DDC Channel (SCA, SCL) may require to +5Vopen drain level at the VGA connector and it may require a pull up resistor on the destination side. Active undershoot-protection circuitry on the data ports of the TS5V522C provide protection for undershoots up to -2V by sensing an undershoot event and ensuring that the switch remains in the proper off state. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pull up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The TS5V522C is high bandwidth analog switches offering a 2:2 dual-graphics crossover solution for VGA signal switching. The device is designed for switching between 2 VGA sources to either of the two destinations within a laptop computer. The TS5V522C integrates 5 very high-frequency 380Mhz (typ) SPDT switches for RGB signals, 2 pairs of level-translating buffer for the HSYNC and VSYNC lines, and integrated ESD protection. The 5 crossover switches can be controlled by either 5V or 3.3V TTL control signals. The TS5V522C would bypass the VGA analog signal to destination with less distortions. DDC Channel (SCA, SCL) may require to +5Vopen drain level at the VGA connector and it may require a pull up resistor on the destination side. Active undershoot-protection circuitry on the data ports of the TS5V522C provide protection for undershoots up to -2V by sensing an undershoot event and ensuring that the switch remains in the proper off state. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pull up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The TSB12LV01B is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12LV01B provides a high-performance IEEE 1394-1995 interface with the capability of transferring data between the 32-bit host bus, the 1394 PHY-link interface, and external devices connected to the local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical (PHY) layer device and is supported by the link-layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. The TSB12LV01B transmits and receives correctly-formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check (CRC). The TSB12LV01B is capable of being cycle master and supports reception of isochronous data on two channels. TSB12LV01B has a generic 32-bit host bus interface, which will connect to most 32-bit hosts. The LLC also provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software. An internal 2K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates the need for external FIFOs. Separate FIFOs can be user configured to support general 1394 receive, asynchronous transmit, and isochronous transmit transfer operations. These functions are accomplished by appropriately sizing the general receive FIFO (GRF), asynchronous transmit FIFO (ATF), and isochronous transmit FIFO (ITF). The TSB12LV01B is a revision of the TSB12LV01A, with feature enhancements and corrections. It is pin for pin compatible with the TSB12LV01A with the restrictions noted below. It is also software compatible with the extensions noted below. All errata items to the TSB12LV01A have been fixed, and the following feature enhancements have been made: However, there are three restrictions that were not present in the TSB12LV01A device: This document is not intended to serve as a tutorial on 1394; users are referred to the IEEE 1394-1995 serial bus standard for detailed information regarding the 1394 high-speed serial bus. The TSB12LV01B is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12LV01B provides a high-performance IEEE 1394-1995 interface with the capability of transferring data between the 32-bit host bus, the 1394 PHY-link interface, and external devices connected to the local bus interface. The 1394 PHY-link interface provides the connection to the 1394 physical (PHY) layer device and is supported by the link-layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and PHY-link interface at rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. The TSB12LV01B transmits and receives correctly-formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check (CRC). The TSB12LV01B is capable of being cycle master and supports reception of isochronous data on two channels. TSB12LV01B has a generic 32-bit host bus interface, which will connect to most 32-bit hosts. The LLC also provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software. An internal 2K-byte memory is provided that can be configured as multiple variable-size FIFOs and eliminates the need for external FIFOs. Separate FIFOs can be user configured to support general 1394 receive, asynchronous transmit, and isochronous transmit transfer operations. These functions are accomplished by appropriately sizing the general receive FIFO (GRF), asynchronous transmit FIFO (ATF), and isochronous transmit FIFO (ITF). The TSB12LV01B is a revision of the TSB12LV01A, with feature enhancements and corrections. It is pin for pin compatible with the TSB12LV01A with the restrictions noted below. It is also software compatible with the extensions noted below. All errata items to the TSB12LV01A have been fixed, and the following feature enhancements have been made: However, there are three restrictions that were not present in the TSB12LV01A device: This document is not intended to serve as a tutorial on 1394; users are referred to the IEEE 1394-1995 serial bus standard for detailed information regarding the 1394 high-speed serial bus.

The TSB14AA1A (TSB14AA1A refers to all three devices: TSB14AA1A, TSB14AA1AI, and TSB14AA1AT) is the second-generation 1394 backplane physical layer device. It is recommended for use in all new designs instead of the first generation TSB14C01A. It provides the physical layer functions needed to implement a single port node in a backplane based 1394 network. The TSB14AA1A provides two pins for transmitting, two for receiving, and two pins to externally control the transceivers for data and strobe. In addition to supporting open-collector drivers, the TSB14AA1A can also support 3-state(1)(high-impedance) drivers. The TSB14AA1A is not designed to drive the backplane directly; this function must be provided externally. The TSB14AA1A is designed to interface with a link-layer controller (LLC), such as the TSB12LV01B, TSB12LV32, TSB12LV21B, etc. The TSB14AA1A requires an external 98.304-MHz reference oscillator input for S100 asynchronous only operation or 49.152-MHz for S50 asynchronous only operation. Two clock select pins (CLK_SEL0, CLK_SEL1) select the speed mode for the TSB14AA1A (see Table 1-1). For S100 operation, the 98.304-MHz reference signal is internally divided to provide the 49.152-MHz system clock signals used to control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. For S50 operation, a 49.152-MHz reference signal is used. This reference signal is internally divided to provide the 24.576-MHz system clock signals for S50 operations. During packet transmit, data bits to be transmitted are received from the LLC on two parallel paths and are latched internally in the TSB14AA1A in synchronization with the system clock. These bits are combined serially, encoded, and transmitted as the outbound data-strobe information stream. During transmit, the encoded data information is transmitted on TDATA, and the encoded strobe information is transmitted on TSTRB. During packet reception, the data information is received on RDATA and strobe information is received on RSTRB. The received data and strobe information is decoded to recover the received clock signal and the serial data bits, which are resynchronized to the local system clock. The serial data bits are split into two parallel streams and sent to the associated LLC. The PHY-Link interface has been made compliant to IEEE 1394a-2000 including timing and transfer of register 0 to the link-layer automatically after every 1394 bus reset. The TSB14AA1A is a 3.3 V device that provides LVCMOS level outputs. The TSB14AA1A is an asynchronous only device. The TSB14AA1A (TSB14AA1A refers to all three devices: TSB14AA1A, TSB14AA1AI, and TSB14AA1AT) is the second-generation 1394 backplane physical layer device. It is recommended for use in all new designs instead of the first generation TSB14C01A. It provides the physical layer functions needed to implement a single port node in a backplane based 1394 network. The TSB14AA1A provides two pins for transmitting, two for receiving, and two pins to externally control the transceivers for data and strobe. In addition to supporting open-collector drivers, the TSB14AA1A can also support 3-state(1)(high-impedance) drivers. The TSB14AA1A is not designed to drive the backplane directly; this function must be provided externally. The TSB14AA1A is designed to interface with a link-layer controller (LLC), such as the TSB12LV01B, TSB12LV32, TSB12LV21B, etc. The TSB14AA1A requires an external 98.304-MHz reference oscillator input for S100 asynchronous only operation or 49.152-MHz for S50 asynchronous only operation. Two clock select pins (CLK_SEL0, CLK_SEL1) select the speed mode for the TSB14AA1A (see Table 1-1). For S100 operation, the 98.304-MHz reference signal is internally divided to provide the 49.152-MHz system clock signals used to control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. For S50 operation, a 49.152-MHz reference signal is used. This reference signal is internally divided to provide the 24.576-MHz system clock signals for S50 operations. During packet transmit, data bits to be transmitted are received from the LLC on two parallel paths and are latched internally in the TSB14AA1A in synchronization with the system clock. These bits are combined serially, encoded, and transmitted as the outbound data-strobe information stream. During transmit, the encoded data information is transmitted on TDATA, and the encoded strobe information is transmitted on TSTRB. During packet reception, the data information is received on RDATA and strobe information is received on RSTRB. The received data and strobe information is decoded to recover the received clock signal and the serial data bits, which are resynchronized to the local system clock. The serial data bits are split into two parallel streams and sent to the associated LLC. The PHY-Link interface has been made compliant to IEEE 1394a-2000 including timing and transfer of register 0 to the link-layer automatically after every 1394 bus reset. The TSB14AA1A is a 3.3 V device that provides LVCMOS level outputs. The TSB14AA1A is an asynchronous only device.