Texas Instruments

The TSB41AB1 provides the digital and analog transceiver functions needed to implement a one-port node in a cable-based IEEE 1394 network. The cable port incorporates one differential line transceiver. The transceiver includes circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB1 is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. The TSB41AB1 requires only an external 24.576-MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. The TSB41AB1 supports an optional isolation barrier between itself and its LLC. When the ISO\ input terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in IEEE 1394a-2000 (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation the ISO\ terminal on the PHY must be high. Data bits to be transmitted through the cable port are received from the LLC on two, four or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41AB1 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair, and the encoded strobe information is transmitted differentially on the TPA cable pair. During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock and sent to the associated LLC. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41AB1 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. TPBIAS is typically VDD–0.2 V when the port is not connected to another node. The line drivers in the TSB41AB1 operate in a high-impedance current mode, and are designed to work with external 112-resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with recommended values of 5 k±1.0%. When the power supply of the TSB41AB1 is off while the twisted-pair cables are connected, the TSB41AB1 transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the device power plane. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDDthrough a 1-kresistor, and SM should be connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are tied high through a 1-k The TSB41AB1 provides the digital and analog transceiver functions needed to implement a one-port node in a cable-based IEEE 1394 network. The cable port incorporates one differential line transceiver. The transceiver includes circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB1 is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. The TSB41AB1 requires only an external 24.576-MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. The TSB41AB1 supports an optional isolation barrier between itself and its LLC. When the ISO\ input terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in IEEE 1394a-2000 (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation the ISO\ terminal on the PHY must be high. Data bits to be transmitted through the cable port are received from the LLC on two, four or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41AB1 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair, and the encoded strobe information is transmitted differentially on the TPA cable pair. During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock and sent to the associated LLC. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41AB1 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. TPBIAS is typically VDD–0.2 V when the port is not connected to another node. The line drivers in the TSB41AB1 operate in a high-impedance current mode, and are designed to work with external 112-resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with recommended values of 5 k±1.0%. When the power supply of the TSB41AB1 is off while the twisted-pair cables are connected, the TSB41AB1 transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the device power plane. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDDthrough a 1-kresistor, and SM should be connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are tied high through a 1-kfilterFind other Other interfaces

The TSB41AB2 provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based IEEE 1394 network. The cable ports incorporate two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB2 is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. The TSB41AB2 requires only an external 24.576-MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. The TSB41AB2 supports an optional isolation barrier between itself and its LLC. When the ISO\ input terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in IEEE 1394a-2000 (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation, the ISO\ terminal on the PHY must be high. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41AB2 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock and sent to the associated LLC. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41AB2 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. TPBIAS is close to VDDwhen an active port is not connected to another node. The line drivers in the TSB41AB2 operate in a high-impedance current mode, and are designed to work with external 112-±1.0%. When the power supply of the TSB41AB2 is off while the twisted-pair cables are connected, the TSB41AB2 transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the device power plane. When the TSB41AB2 is used with one of the ports not brought out to a connector, the twisted-pair terminals of the unused port must be terminated for reliable operation. For each unused port, the TPB+ and TPB– terminals should be tied together and then pulled to ground, or the TPB+ and TPB– terminals should be connected to the suggested termination network (see Figure 5). The TPA+ and TPA– and TPBIAS terminals of an unused port may be left unconnected. The TPBIAS terminal should be connected to a 1-µF capacitor to ground or left floating. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDDthrough a 1-kresistor, and SM should be connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are tied high through a 1-kresistor or hardwired low as a function of the equipment design. The PC0–PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager (IRM) or bus manager (BM). The TSB41AB2 supports suspend/resume as defined in IEEE 1394a-2000 specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low-power state (suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBIAS. When ports of the TSB41AB2 are suspended, all circuits except the band gap reference generator and bias detection circuits are powered down, resulting in significant power savings. For additional details of suspend/resume operation see IEEE 1394a-2000. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET\ input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBIAS output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The cable-not-active (CNA) output terminal is asserted high when there are no twisted-pair cable ports receiving incoming bias (that is, they are either disconnected or suspended), and can be used along with LPS to determine when to power down the TSB41AB2. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET\ terminal to force a reset of the TSB41AB2 internal logic. The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the Application Information section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise. When the TSB41AB2 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41AB2 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it to normal operation. When the PHY-LLC interface is in the low-power disabled state, the TSB41AB2 automatically enters a low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41AB2 disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the port (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt enable bit cleared. The TSB41AB2 exits the low-power mode when the LPS input is asserted high or when a port event occurs. This requires that the TSB41AB2 become active in order to respond to the event or to notify the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes active (and the PHY-LLC interface is initialized and become operative) within 7.3 ms after LPS is asserted high when the TSB41AB2 is in the low-power mode. The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON to be active. The TSB41AB2 provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based IEEE 1394 network. The cable ports incorporate two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB2 is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. The TSB41AB2 requires only an external 24.576-MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. The TSB41AB2 supports an optional isolation barrier between itself and its LLC. When the ISO\ input terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in IEEE 1394a-2000 (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation, the ISO\ terminal on the PHY must be high. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41AB2 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock and sent to the associated LLC. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41AB2 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. TPBIAS is close to VDDwhen an active port is not connected to another node. The line drivers in the TSB41AB2 operate in a high-impedance current mode, and are designed to work with external 112-±1.0%. When the power supply of the TSB41AB2 is off while the twisted-pair cables are connected, the TSB41AB2 transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the device power plane. When the TSB41AB2 is used with one of the ports not brought out to a connector, the twisted-pair terminals of the unused port must be terminated for reliable operation. For each unused port, the TPB+ and TPB– terminals should be tied together and then pulled to ground, or the TPB+ and TPB– terminals should be connected to the suggested termination network (see Figure 5). The TPA+ and TPA– and TPBIAS terminals of an unused port may be left unconnected. The TPBIAS terminal should be connected to a 1-µF capacitor to ground or left floating. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDDthrough a 1-kresistor, and SM should be connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are tied high through a 1-kresistor or hardwired low as a function of the equipment design. The PC0–PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager (IRM) or bus manager (BM). The TSB41AB2 supports suspend/resume as defined in IEEE 1394a-2000 specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low-power state (suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBIAS. When ports of the TSB41AB2 are suspended, all circuits except the band gap reference generator and bias detection circuits are powered down, resulting in significant power savings. For additional details of suspend/resume operation see IEEE 1394a-2000. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET\ input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBIAS output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The cable-not-active (CNA) output terminal is asserted high when there are no twisted-pair cable ports receiving incoming bias (that is, they are either disconnected or suspended), and can be used along with LPS to determine when to power down the TSB41AB2. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET\ terminal to force a reset of the TSB41AB2 internal logic. The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the Application Information section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise. When the TSB41AB2 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41AB2 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it to normal operation. When the PHY-LLC interface is in the low-power disabled state, the TSB41AB2 automatically enters a low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41AB2 disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the port (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt enable bit cleared. The TSB41AB2 exits the low-power mode when the LPS input is asserted high or when a port event occurs. This requires that the TSB41AB2 become active in order to respond to the event or to notify the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes active (and the PHY-LLC interface is initialized and become operative) within 7.3 ms after LPS is asserted high when the TSB41AB2 is in the low-power mode. The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON to be active.

The TSB41AB3 provides the digital and analog transceiver functions required to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB3 is designed to interface with a line layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. The TSB41AB3 requires only an external 24.576-MHz crystal as a reference. An external clock may be used instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. The TSB41AB3 supports an optional isolation barrier between itself and its LLC. When the ISO input terminal is tied high, the LLC interface outputs behave normally. When the ISO terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in the 1394a-2000 Supplement (section 5.9.4) (hereafter referred to as Annex J type isolation). To operate with TI bus holder isolation, the ISO terminal on the PHY must be high. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths (depending on the requested transmission speed). They are latched internally in the TSB41AB3 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 392.216 Mbits/s (referred to as S100, S200, and S400 speed, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock, and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41AB3 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. The line drivers in the TSB41AB3, operating in a high-impedance current mode, are designed to work with external 112-line-termination resistor networks in order to match the 110-cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B terminals is coupled to ground through a parallel R-C network with recommended values of 5 kand 220 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.34 k±1%. When the power supply of the TSB41AB3 is off while the twisted-pair cables are connected, the TSB41AB3 transmitter and receiver circuitry presents a high-impedance signal to the cable and does not load the TPBIAS voltage at the other end of the cable. When the TSB41AB3 is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB. terminals can be tied together and then pulled to ground through a 1-kresistor, or the TPB+ and TPB– terminals can be connected to the suggested termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBias terminal can be connected to a 1-µF capacitor to ground or left floating. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, it is recommended that the TESTM terminal be connected to VDDthrough a 1-kresistor, and SE be tied to ground through a 1-kresistor, while SM is connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet and are tied high through a 1-kresistor or hardwired low as a function of the equipment design. The PC0–PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender either isochronous resource manager (IRM) or for bus manager (BM). The TSB41AB3 supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low-power conservation state (suspended state) while maintaining a port-to-port connection between 1394 bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBias. When all three ports of the TSB41AB3 are suspended, all circuits except the band gap reference generator and bias detection circuits are powered down resulting in significant power savings. For additional details of suspend/resume operation refer to the 1394a-2000 specification. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when theRESETinput terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The CNA (cable-not-active) terminal provides a high when there are no twisted-pair cable ports receiving incoming bias (i.e., they are either disconnected or suspended) and can be used along with LPS to determine when to power down the TSB41AB3. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET terminal so as to force a reset of the TSB41AB3 internal logic. The link power status (LPS) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in theAPPLICATION INFORMATIONsection) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise. When the TSB41AB3 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41AB3 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY.LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it to normal operation. When the PHY-LLC interface is in the low-power disabled state, the TSB41AB3 automatically enters a low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41AB3 disables its internal clock generators and also disables various voltage and current reference circuits, depending on the state of the ports (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (the ultralow power sleep mode) is attained when all ports are either disconnected, or disabled with the port’s interrupt enable bit cleared. The TSB41AB3 exits the low-power mode when the LPS input is asserted high or when a port event occurs which requires that the TSB41AB3 become active in order to respond to the event or to notify the LLC of the event (incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port). The SYSCLK output becomes active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high when the TSB41AB3 is in the low-power mode. The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus-reset occurs unless a PHY interrupt condition exists which otherwise causes C/LKON to be active. The TSB41AB3 provides the digital and analog transceiver functions required to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB3 is designed to interface with a line layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. The TSB41AB3 requires only an external 24.576-MHz crystal as a reference. An external clock may be used instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. The TSB41AB3 supports an optional isolation barrier between itself and its LLC. When the ISO input terminal is tied high, the LLC interface outputs behave normally. When the ISO terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in the 1394a-2000 Supplement (section 5.9.4) (hereafter referred to as Annex J type isolation). To operate with TI bus holder isolation, the ISO terminal on the PHY must be high. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths (depending on the requested transmission speed). They are latched internally in the TSB41AB3 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 392.216 Mbits/s (referred to as S100, S200, and S400 speed, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock, and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41AB3 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. The line drivers in the TSB41AB3, operating in a high-impedance current mode, are designed to work with external 112-line-termination resistor networks in order to match the 110-cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B terminals is coupled to ground through a parallel R-C network with recommended values of 5 kand 220 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.34 k±1%. When the power supply of the TSB41AB3 is off while the twisted-pair cables are connected, the TSB41AB3 transmitter and receiver circuitry presents a high-impedance signal to the cable and does not load the TPBIAS voltage at the other end of the cable. When the TSB41AB3 is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB. terminals can be tied together and then pulled to ground through a 1-kresistor, or the TPB+ and TPB– terminals can be connected to the suggested termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBias terminal can be connected to a 1-µF capacitor to ground or left floating. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, it is recommended that the TESTM terminal be connected to VDDthrough a 1-kresistor, and SE be tied to ground through a 1-kresistor, while SM is connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet and are tied high through a 1-kresistor or hardwired low as a function of the equipment design. The PC0–PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender either isochronous resource manager (IRM) or for bus manager (BM). The TSB41AB3 supports suspend/resume as defined in the IEEE 1394a-2000 specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low-power conservation state (suspended state) while maintaining a port-to-port connection between 1394 bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBias. When all three ports of the TSB41AB3 are suspended, all circuits except the band gap reference generator and bias detection circuits are powered down resulting in significant power savings. For additional details of suspend/resume operation refer to the 1394a-2000 specification. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when theRESETinput terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The CNA (cable-not-active) terminal provides a high when there are no twisted-pair cable ports receiving incoming bias (i.e., they are either disconnected or suspended) and can be used along with LPS to determine when to power down the TSB41AB3. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET terminal so as to force a reset of the TSB41AB3 internal logic. The link power status (LPS) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in theAPPLICATION INFORMATIONsection) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise. When the TSB41AB3 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41AB3 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY.LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it to normal operation. When the PHY-LLC interface is in the low-power disabled state, the TSB41AB3 automatically enters a low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41AB3 disables its internal clock generators and also disables various voltage and current reference circuits, depending on the state of the ports (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (the ultralow power sleep mode) is attained when all ports are either disconnected, or disabled with the port’s interrupt enable bit cleared. The TSB41AB3 exits the low-power mode when the LPS input is asserted high or when a port event occurs which requires that the TSB41AB3 become active in order to respond to the event or to notify the LLC of the event (incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port). The SYSCLK output becomes active (and the PHY-LLC interface is initialized and becomes operative) within 7.3 ms after LPS is asserted high when the TSB41AB3 is in the low-power mode. The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus-reset occurs unless a PHY interrupt condition exists which otherwise causes C/LKON to be active.

The TSB41BA3D provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41BA3D interfaces with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It can also be connected via cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2. The TSB41BA3D is powered by a single 3.3-V supply. The core voltage supply is supplied by an internal voltage regulator to the PLLVDD-CORE and DVDD-CORE terminals. To protect the phase-locked loop (PLL) from noise, the PLLVDD-CORE terminals must be separately decoupled from the DVDD-CORE terminals. The PLLVDD-CORE terminals are decoupled with 1-µF and smaller decoupling capacitors and the DVDD-CORE terminals are separately decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE must be implemented by separate power supply rails or planes. The TSB41BA3D can be powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-CORE and DVDD-CORE terminals to the requirements in therecommended operating conditionssection of this data sheet. The PLLVDD-CORE terminals must be separated from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1-µF and smaller decoupling capacitors and the DVDD-CORE terminals separately decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE can be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by a filter network to keep noise from the PLLVDD-CORE supply. The TSB41BA3D requires an external 49.152-MHz crystal to generate a reference clock. The external clock drives an internal PLL, which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices and is used for resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE 1394a-2000 standard. A 98.304-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE 1394b-2002 standard. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are latched internally, combined serially, encoded, and transmitted at 98.304, 122.78, 196.608, 245.76, 393.216, or 491.52 Mbps (referred to as S100, S100B, S200, S200B, S400, or S400B speed, respectively) as the outbound information stream. The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the 1394b-2002 standard. The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When any of the three ports is connected to a 1394a-2000-compliant device, the cable interface on that port operates in the 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b-compliant node, the cable interface on that port operates per the 1394b-2002 standard at S100B, S200B, or S400B speed. The TSB41BA3D automatically determines the correct cable interface connection method for the bilingual ports. NOTE:The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal selects the PHY-link interface mode of operation and affects the arbitration modes on the cable. When the BMODE terminal is deasserted, the PHY-link interface is placed in 1394a-2000 mode and BOSS arbitration is disabled. When the BMODE terminal is asserted, the PHY-link interface is placed in 1394b-2002 mode and BOSS arbitration is enabled. During packet reception, the serial data bits are split into 2-, 4-, or 8-bit parallel streams (depending on the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock, and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected and active cable ports. Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration when connected to a 1394a-2000-compliant device. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage. When connected to a 1394a-2000-compliant node, the TSB41BA3D provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. The line drivers in the TSB41BA3D are designed to work with external 112-termination resistor networks in order to match the 110-cable impedance. One termination network is required at each end of a twisted-pair cable. Each network is composed of a pair of series-connected ~56-resistors. The midpoint of the pair of resistors that is connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the TPB terminals is coupled to ground through a parallel RC network with recommended values of 5 kand 270 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. When the power supply of the TSB41BA3D is off while the twisted-pair cables are connected, the TSB41BA3D transmitter and receiver circuitry present a high-impedance signal to the cable that does not load the device at the other end of the cable. When the TSB41BA3D is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the preferred method is for the port to be forced to the 1394a-only mode (data-strobe-only mode, DS), then the TPB+ and TPB– terminals can be tied together and then pulled to ground; or the TPB+ and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal can be left unconnected. If the port is left in bilingual (Bi) mode, then the TPB+ and TPB– terminals can be left unconnected or the TPB+ and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal can be left unconnected. If the port is left in a forced 1394b Beta-only (B1, B2, or B4) mode, then the TPB+ and TPB– terminals can be left unconnected or the TPB+ and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal must be pulled to ground through a 1.2-kor smaller resistor. To operate a port as a 1394b bilingual port, the speed/mode selections terminals (S5_LKON, S4, S3, S2_PC0, S1_PC1, and S0_PC2) need to be pulled to VCCor ground through a 1-kresistor. The port must be operated in the 1394b bilingual mode whenever a 1394b bilingual or a 1394b Beta-only connector is connected to the port. To operate the port as a 1394a-only port, the speed/mode selection terminals must be configured correctly to force 1394a-2000-only operation on that port. The only time the port must be forced to the data-strobe-only mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode is provided to ensure that 1394b signaling is never sent across a 1394a cable. NOTE:A bilingual port can only connect to a 1394b-only port that operates at S400b. It cannot establish a connection to a S200b or S100b port. A port that has been forced to S400b (B4) can connect to a 1394b-only port at S400b (B4) or S200b (B2) or S100b (B1). A port that has been forced to S200b can connect to a 1394b-only port at S200b or S100b. A port that has been forced to S100b can only connect to a 1394b-only port at S100b. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal must be connected to VDDthrough a 1-kresistor. The SE and SM terminals must be tied to ground through a 1-kresistor. Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They can be pulled high through a 1-kresistor or hardwired low as a function of the equipment design. In some speed/mode selections the S2_PC0, S1_PC1, and S0_PC2 terminals indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable); see . The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the TSB41BA3D, this bit can only be set by a write to the PHY register set. If a node is a contender for IRM or BM, then the node software must set this bit in the PHY register set. The LPS (link power status) terminal works with the S5_LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used with the LCtrl bit (see and in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). NOTE:The TSB41BA3D does not have a cable-not-active (CNA) terminal. To achieve a similar function, the individual PHY ports can be set up to issue interrupts whenever the port changes state. If the LPS terminal is low, then this generates a link-on (LKON) output clock. See register bits PIE, PEI, and WDIE along with the individual interrupt bits. The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB41BA3D detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB41BA3D continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB41BA3D issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible). The PHY uses the S5_LKON terminal to notify the LLC to power up and become active. When activated, the output S5_LKON signal is a square wave. The PHY activates the S5_LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as previously described, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the S5_LKON output when the LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the S5_LKON output when a bus reset occurs, unless a PHY interrupt condition exists which would otherwise cause S5_LKON to be active. If the PHY is power-cycled and the power class is 0 through 4, then the PHY asserts S5_LKON for approximately 167 µs or until both the LPS is active and the LCtrl bit is 1. The TSB41BA3D provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41BA3D interfaces with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It can also be connected via cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2. The TSB41BA3D is powered by a single 3.3-V supply. The core voltage supply is supplied by an internal voltage regulator to the PLLVDD-CORE and DVDD-CORE terminals. To protect the phase-locked loop (PLL) from noise, the PLLVDD-CORE terminals must be separately decoupled from the DVDD-CORE terminals. The PLLVDD-CORE terminals are decoupled with 1-µF and smaller decoupling capacitors and the DVDD-CORE terminals are separately decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE must be implemented by separate power supply rails or planes. The TSB41BA3D can be powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-CORE and DVDD-CORE terminals to the requirements in therecommended operating conditionssection of this data sheet. The PLLVDD-CORE terminals must be separated from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1-µF and smaller decoupling capacitors and the DVDD-CORE terminals separately decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE can be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by a filter network to keep noise from the PLLVDD-CORE supply. The TSB41BA3D requires an external 49.152-MHz crystal to generate a reference clock. The external clock drives an internal PLL, which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices and is used for resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE 1394a-2000 standard. A 98.304-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE 1394b-2002 standard. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are latched internally, combined serially, encoded, and transmitted at 98.304, 122.78, 196.608, 245.76, 393.216, or 491.52 Mbps (referred to as S100, S100B, S200, S200B, S400, or S400B speed, respectively) as the outbound information stream. The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the 1394b-2002 standard. The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When any of the three ports is connected to a 1394a-2000-compliant device, the cable interface on that port operates in the 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b-compliant node, the cable interface on that port operates per the 1394b-2002 standard at S100B, S200B, or S400B speed. The TSB41BA3D automatically determines the correct cable interface connection method for the bilingual ports. NOTE:The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal selects the PHY-link interface mode of operation and affects the arbitration modes on the cable. When the BMODE terminal is deasserted, the PHY-link interface is placed in 1394a-2000 mode and BOSS arbitration is disabled. When the BMODE terminal is asserted, the PHY-link interface is placed in 1394b-2002 mode and BOSS arbitration is enabled. During packet reception, the serial data bits are split into 2-, 4-, or 8-bit parallel streams (depending on the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock, and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected and active cable ports. Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration when connected to a 1394a-2000-compliant device. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage. When connected to a 1394a-2000-compliant node, the TSB41BA3D provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. The line drivers in the TSB41BA3D are designed to work with external 112-termination resistor networks in order to match the 110-cable impedance. One termination network is required at each end of a twisted-pair cable. Each network is composed of a pair of series-connected ~56-resistors. The midpoint of the pair of resistors that is connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the TPB terminals is coupled to ground through a parallel RC network with recommended values of 5 kand 270 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. When the power supply of the TSB41BA3D is off while the twisted-pair cables are connected, the TSB41BA3D transmitter and receiver circuitry present a high-impedance signal to the cable that does not load the device at the other end of the cable. When the TSB41BA3D is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the preferred method is for the port to be forced to the 1394a-only mode (data-strobe-only mode, DS), then the TPB+ and TPB– terminals can be tied together and then pulled to ground; or the TPB+ and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal can be left unconnected. If the port is left in bilingual (Bi) mode, then the TPB+ and TPB– terminals can be left unconnected or the TPB+ and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal can be left unconnected. If the port is left in a forced 1394b Beta-only (B1, B2, or B4) mode, then the TPB+ and TPB– terminals can be left unconnected or the TPB+ and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal must be pulled to ground through a 1.2-kor smaller resistor. To operate a port as a 1394b bilingual port, the speed/mode selections terminals (S5_LKON, S4, S3, S2_PC0, S1_PC1, and S0_PC2) need to be pulled to VCCor ground through a 1-kresistor. The port must be operated in the 1394b bilingual mode whenever a 1394b bilingual or a 1394b Beta-only connector is connected to the port. To operate the port as a 1394a-only port, the speed/mode selection terminals must be configured correctly to force 1394a-2000-only operation on that port. The only time the port must be forced to the data-strobe-only mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode is provided to ensure that 1394b signaling is never sent across a 1394a cable. NOTE:A bilingual port can only connect to a 1394b-only port that operates at S400b. It cannot establish a connection to a S200b or S100b port. A port that has been forced to S400b (B4) can connect to a 1394b-only port at S400b (B4) or S200b (B2) or S100b (B1). A port that has been forced to S200b can connect to a 1394b-only port at S200b or S100b. A port that has been forced to S100b can only connect to a 1394b-only port at S100b. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal must be connected to VDDthrough a 1-kresistor. The SE and SM terminals must be tied to ground through a 1-kresistor. Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They can be pulled high through a 1-kresistor or hardwired low as a function of the equipment design. In some speed/mode selections the S2_PC0, S1_PC1, and S0_PC2 terminals indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable); see . The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the TSB41BA3D, this bit can only be set by a write to the PHY register set. If a node is a contender for IRM or BM, then the node software must set this bit in the PHY register set. The LPS (link power status) terminal works with the S5_LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used with the LCtrl bit (see and in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). NOTE:The TSB41BA3D does not have a cable-not-active (CNA) terminal. To achieve a similar function, the individual PHY ports can be set up to issue interrupts whenever the port changes state. If the LPS terminal is low, then this generates a link-on (LKON) output clock. See register bits PIE, PEI, and WDIE along with the individual interrupt bits. The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB41BA3D detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB41BA3D continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB41BA3D issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible). The PHY uses the S5_LKON terminal to notify the LLC to power up and become active. When activated, the output S5_LKON signal is a square wave. The PHY activates the S5_LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as previously described, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the S5_LKON output when the LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the S5_LKON output when a bus reset occurs, unless a PHY interrupt condition exists which would otherwise cause S5_LKON to be active. If the PHY is power-cycled and the power class is 0 through 4, then the PHY asserts S5_LKON for approximately 167 µs or until both the LPS is active and the LCtrl bit is 1.

The TSB41LV06A provides the digital and analog transceiver functions needed to implement a six-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41LV06A is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. The TSB41LV06A requires only an external 24.576 MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152 MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. The TSB41LV06A supports an optional isolation barrier between itself and its LLC. When the ISO\ input terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in the P1394a Supplement (section 5.9.4) (hereafter referred to as Annex J type isolation). To operate with TI bus holder isolation the ISO\ terminal on the PHY must be high. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41LV06A in synchronization with the 49.152 MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two, four, or eight bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41LV06A provides a 1.86 V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains six independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 uF. The line drivers in the TSB41LV06A operate in a high-impedance current mode, and are designed to work with external 112-line-termination resistor networks in order to match the 110-cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with recommended values of 5 kand 220 pF. The values of the external line termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.3-k±1%. This may be accomplished by placing a 6.34-k±1% resistor in parallel with a 1-Mresistor. When the power supply of the TSB41LV06A is off while the twisted-pair cables are connected, the TSB41LV06A transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable. When the TSB41LV06A is used with one or more of the ports not brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB- terminals should be tied together and then pulled to ground, or the TPB+ and TPB- terminals should be connected to the suggested termination network. The TPA+ and TPA- and TPBIAS terminals of an unused port may be left unconnected. The TPBIAS terminal may be connected to a 1 uF capacitor to ground or left floating. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDD, SE should be tied to ground through a 1-kresistor, while SM should be connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are hardwired high or low as a function of the equipment design. The PC0-PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 1 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager (IRM) or bus manager (BM). The TSB41LV06A supports suspend/resume as defined in the IEEE P1394a specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low power conservation state (suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBias. When all six ports of the TSB41LV06A are suspended, all circuits except the bandgap reference generator and bias detection circuits are powered down resulting in significant power savings. For additional details of suspend/resume operation refer to the P1394a specification. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power-down (when the PD input terminal is asserted high), during reset (when the RESET\ input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The CNA (cable-not-active) output terminal is asserted high when there are no twisted-pair cable ports receiving incoming bias (i.e., they are either disconnected or suspended), and can be used along with LPS to determine when to power down the TSB41LV06A. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET\ terminal so as to force a reset of the TSB41LV06A internal logic. The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). The LPS input is considered inactive if it remains low for more than 2.6 us and is considered active otherwise. When the TSB41LV06A detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 us, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41LV06A continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and return it to normal operation. When the PHY-LLC interface is in the low-power disabled state, the TSB41LV06A automatically enters a low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41LV06A disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the ports (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (theultralow-power sleepmode) is attained when all ports are either disconnected, or disabled with the port's interrupt enable bit cleared. The TSB41LV06A exits the low-power mode when the LPS input is asserted high or when a port event occurs which requires that the TSB41LV06A become active in order to respond to the event or to notify the LLC of the event (e.g., incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes active (and the PHY-LLC interface initializes and becomes operative) within 7.3 ms after LPS is asserted high when the TSB41LV06A is in the low-power mode. The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163 ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus-reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON to be active. The TSB41LV06A provides the digital and analog transceiver functions needed to implement a six-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41LV06A is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. The TSB41LV06A requires only an external 24.576 MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152 MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. The TSB41LV06A supports an optional isolation barrier between itself and its LLC. When the ISO\ input terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in the P1394a Supplement (section 5.9.4) (hereafter referred to as Annex J type isolation). To operate with TI bus holder isolation the ISO\ terminal on the PHY must be high. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41LV06A in synchronization with the 49.152 MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two, four, or eight bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41LV06A provides a 1.86 V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains six independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 uF. The line drivers in the TSB41LV06A operate in a high-impedance current mode, and are designed to work with external 112-line-termination resistor networks in order to match the 110-cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with recommended values of 5 kand 220 pF. The values of the external line termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.3-k±1%. This may be accomplished by placing a 6.34-k±1% resistor in parallel with a 1-Mresistor. When the power supply of the TSB41LV06A is off while the twisted-pair cables are connected, the TSB41LV06A transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable. When the TSB41LV06A is used with one or more of the ports not brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB- terminals should be tied together and then pulled to ground, or the TPB+ and TPB- terminals should be connected to the suggested termination network. The TPA+ and TPA- and TPBIAS terminals of an unused port may be left unconnected. The TPBIAS terminal may be connected to a 1 uF capacitor to ground or left floating. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDD, SE should be tied to ground through a 1-kresistor, while SM should be connected directly to ground. Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are hardwired high or low as a function of the equipment design. The PC0-PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 1 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender for either isochronous resource manager (IRM) or bus manager (BM). The TSB41LV06A supports suspend/resume as defined in the IEEE P1394a specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low power conservation state (suspended state) while maintaining a port-to-port connection between bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBias. When all six ports of the TSB41LV06A are suspended, all circuits except the bandgap reference generator and bias detection circuits are powered down resulting in significant power savings. For additional details of suspend/resume operation refer to the P1394a specification. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power-down (when the PD input terminal is asserted high), during reset (when the RESET\ input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The CNA (cable-not-active) output terminal is asserted high when there are no twisted-pair cable ports receiving incoming bias (i.e., they are either disconnected or suspended), and can be used along with LPS to determine when to power down the TSB41LV06A. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pulldown is activated on the RESET\ terminal so as to force a reset of the TSB41LV06A internal logic. The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LLC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). The LPS input is considered inactive if it remains low for more than 2.6 us and is considered active otherwise. When the TSB41LV06A detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 us, the PHY-LLC interface is put into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also held in the disabled state during hardware reset. The TSB41LV06A continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and return it to normal operation. When the PHY-LLC interface is in the low-power disabled state, the TSB41LV06A automatically enters a low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41LV06A disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the ports (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (theultralow-power sleepmode) is attained when all ports are either disconnected, or disabled with the port's interrupt enable bit cleared. The TSB41LV06A exits the low-power mode when the LPS input is asserted high or when a port event occurs which requires that the TSB41LV06A become active in order to respond to the event or to notify the LLC of the event (e.g., incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes active (and the PHY-LLC interface initializes and becomes operative) within 7.3 ms after LPS is asserted high when the TSB41LV06A is in the low-power mode. The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163 ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus-reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON to be active.

Consumer Electronics Link (ceLynx) is a high-performance 1394 link layer device designed specifically to support advanced consumer electronics applications, particularly those applications which require the transmission of Moving Picture Expert Group 2 (MPEG2) transport streams and encryption/decryption of those streams across a 1394 network. The device supports both digital video broadcasting (DVB) and DirecTV™ type MPEG2 streams using the digital transmission content protection method (DTCP) method of encryption, as well as digital video (DV) encoded streams. The ceLynx supports both the IEC 61883 standard for DVB and DV streams over 1394 and the 1394 Trade Association standard for DirecTV over 1394. The ceLynx is also versatile enough to handle asynchronous data and asynchronous streams. A key feature of the ceLynx is its ability to handle multiple data type streams simultaneously; the user may transport DVB, DirecTV, DV data streams, and asynchronous datasimultaneously. The ceLynx can also support multiple streams of the same data type simultaneously, (for example, transmit or receive two DVB transport streams or two DV streams). The ceLynx is full duplex, allowing simultaneous playback and recording of audio/video data. Full duplex support also includes the capability of using the DTCP method, simultaneously using the two embedded M6 cipher modules. The large internal 8-Kbyte FIFO is very flexible, allowing the user to partition it into eight independent first in first out (FIFOs) and allowing the user to determine the exact configuration of each of these FIFOs to fit the application. Advanced features have been added to support program ID (PID) filtering and packet insertions. The ceLynx is also designed to interface seamlessly with popular MPEG2 decoder chipsets. This decreases the design-in effort of customers when using these popular chipsets. Consumer Electronics Link (ceLynx) is a high-performance 1394 link layer device designed specifically to support advanced consumer electronics applications, particularly those applications which require the transmission of Moving Picture Expert Group 2 (MPEG2) transport streams and encryption/decryption of those streams across a 1394 network. The device supports both digital video broadcasting (DVB) and DirecTV™ type MPEG2 streams using the digital transmission content protection method (DTCP) method of encryption, as well as digital video (DV) encoded streams. The ceLynx supports both the IEC 61883 standard for DVB and DV streams over 1394 and the 1394 Trade Association standard for DirecTV over 1394. The ceLynx is also versatile enough to handle asynchronous data and asynchronous streams. A key feature of the ceLynx is its ability to handle multiple data type streams simultaneously; the user may transport DVB, DirecTV, DV data streams, and asynchronous datasimultaneously. The ceLynx can also support multiple streams of the same data type simultaneously, (for example, transmit or receive two DVB transport streams or two DV streams). The ceLynx is full duplex, allowing simultaneous playback and recording of audio/video data. Full duplex support also includes the capability of using the DTCP method, simultaneously using the two embedded M6 cipher modules. The large internal 8-Kbyte FIFO is very flexible, allowing the user to partition it into eight independent first in first out (FIFOs) and allowing the user to determine the exact configuration of each of these FIFOs to fit the application. Advanced features have been added to support program ID (PID) filtering and packet insertions. The ceLynx is also designed to interface seamlessly with popular MPEG2 decoder chipsets. This decreases the design-in effort of customers when using these popular chipsets.