| Integrated Circuits (ICs) | 3 | Obsolete | |
74BCT282710-ch, 4.5-V to 5.5-V buffers with 3-state outputs | Integrated Circuits (ICs) | 4 | Active | These 10-bit buffers and bus drivers are specifically designed to drive the capacitive input characteristics of MOS DRAMs. They provide high-performance bus interface for wide data paths or buses carrying parity.
The 3-state control gate is a 2-input AND gate with active-low inputs so if either output-enable (or) input is high, all ten outputs are in the high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down.
The SN54BCT2827C is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT2827C is characterized for operation from 0°C to 70°C.
These 10-bit buffers and bus drivers are specifically designed to drive the capacitive input characteristics of MOS DRAMs. They provide high-performance bus interface for wide data paths or buses carrying parity.
The 3-state control gate is a 2-input AND gate with active-low inputs so if either output-enable (or) input is high, all ten outputs are in the high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down.
The SN54BCT2827C is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT2827C is characterized for operation from 0°C to 70°C. |
| Integrated Circuits (ICs) | 2 | Obsolete | |
| Flip Flops | 1 | Obsolete | |
| Integrated Circuits (ICs) | 1 | Obsolete | |
| Logic | 3 | Obsolete | |
| Buffers, Drivers, Receivers, Transceivers | 3 | Active | The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error () output will indicate whether or not an error in the B data has occurred. The output-enable (,) inputs can be used to disable the device so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error () flag.can be either passed, sampled, stored, or cleared from the latch using the latch-enable () and clear () control inputs. When bothandare low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C.
The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error () output will indicate whether or not an error in the B data has occurred. The output-enable (,) inputs can be used to disable the device so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error () flag.can be either passed, sampled, stored, or cleared from the latch using the latch-enable () and clear () control inputs. When bothandare low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C. |
| Buffers, Drivers, Receivers, Transceivers | 2 | Active | |
| Buffers, Drivers, Receivers, Transceivers | 3 | Active | |
| Logic | 1 | Obsolete | |
