TMDS341A1.65-Gbps 3-to-1 DVI/HDMI 1.3a mux | Specialized | 4 | Active | The TMDS341A is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug detector, and an I2C interface are supported on each port. Each TMDS channel allows signaling rates up to 2.25 Gbps.
The active source is selected by configuring source selectors, S1, S2, and S3. The selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I2C interface of the selected input port is linked to the I2C interface of the output port, and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused ports, the I2C interfaces are isolated, and the HPD pins are kept low.
Termination resistors (50-), pulled up to VCC, are integrated at each receiver input pin. External terminations are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard. When the output is connected to a standard TMDS termination andOEis high, the output is high impedance.
The TMDS341A provides fixed 8-dB input equalization and selectable 3-dB output de-emphasis to optimize system performance through 5-meter or longer DVI compliant cables. The device is characterized for operation from 0°C to 70°C.
The TMDS341A is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug detector, and an I2C interface are supported on each port. Each TMDS channel allows signaling rates up to 2.25 Gbps.
The active source is selected by configuring source selectors, S1, S2, and S3. The selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I2C interface of the selected input port is linked to the I2C interface of the output port, and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused ports, the I2C interfaces are isolated, and the HPD pins are kept low.
Termination resistors (50-), pulled up to VCC, are integrated at each receiver input pin. External terminations are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard. When the output is connected to a standard TMDS termination andOEis high, the output is high impedance.
The TMDS341A provides fixed 8-dB input equalization and selectable 3-dB output de-emphasis to optimize system performance through 5-meter or longer DVI compliant cables. The device is characterized for operation from 0°C to 70°C. |
TMDS3512.5-Gbps 3-to1 DVI/HDMI1.3a mux | Interface | 1 | Active | The TMDS351 is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 2.5 Gbps to allow 1080p resolution in 12-bit color depth.
When S1 is high and S2 is low, all input terminations are disconnected, TMDS inputs are high impedance with standard TMDS terminations, all internal MOSFETs are turned off to disable the DDC links, and all HPD outputs are connected to the HPD_SINK. This allows the initiation of the HDMI physical address discovery process.
Termination resistors (50-Ω), pulled up to VCC, are integrated at each TMDS receiver input. External terminations are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard.
The TMDS351 provides two levels of receiver input equalization for different ranges of cable lengths. Each TMDS receiver owns frequency responsive equalization circuits. When EQ sets low, the receiver supports the input connection in short range HDMI cables. When EQ sets high, the receiver supports the input connection in long range HDMI cables. The TMDS351 supports power saving operation. When a system is under standby mode and there is no digital audio/visual content from a connected source, the 3.3-V supply voltage, VCC, can be powered off to minimize power consumption from the TMDS inputs, outputs, and internal switching circuits. The HPD, DDC, and source selection circuits are powered up by the 5-V supply voltage, VDD, to maintain the system hot plug detect response, the DDC link from the selected source to the sink under system standby operation. The device is characterized for operation from 0°C to 70°C.
The TMDS351 is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 2.5 Gbps to allow 1080p resolution in 12-bit color depth.
When S1 is high and S2 is low, all input terminations are disconnected, TMDS inputs are high impedance with standard TMDS terminations, all internal MOSFETs are turned off to disable the DDC links, and all HPD outputs are connected to the HPD_SINK. This allows the initiation of the HDMI physical address discovery process.
Termination resistors (50-Ω), pulled up to VCC, are integrated at each TMDS receiver input. External terminations are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard.
The TMDS351 provides two levels of receiver input equalization for different ranges of cable lengths. Each TMDS receiver owns frequency responsive equalization circuits. When EQ sets low, the receiver supports the input connection in short range HDMI cables. When EQ sets high, the receiver supports the input connection in long range HDMI cables. The TMDS351 supports power saving operation. When a system is under standby mode and there is no digital audio/visual content from a connected source, the 3.3-V supply voltage, VCC, can be powered off to minimize power consumption from the TMDS inputs, outputs, and internal switching circuits. The HPD, DDC, and source selection circuits are powered up by the 5-V supply voltage, VDD, to maintain the system hot plug detect response, the DDC link from the selected source to the sink under system standby operation. The device is characterized for operation from 0°C to 70°C. |
TMDS361B3-Gbps 3-to-1 HDMI/DVI mux with adaptive equalization and enhanced jitter performance | Linear | 2 | Active | The TMDS361B is a three-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to three DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth. TMDS361B is not intended for source side applications such as external switch boxes.
The TMDS361B provides an adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps.
When any of the input ports are selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state.
The TMDS361B is designed to be controlled via a local I2C interface or GPIO interface based on the status of the I2C_SEL pin. The local I2C interface in TMDS361B is a slave-only I2C interface. (See the section.)
I2C Mode: When the I2C_SEL pin is set low, the device is in I2C mode. With local I2C, the interface port status can be read and the advanced configurations of the device such as TMDS output edge rate control, DDC I2C buffer output-voltage-select (OVS) settings (See the for detailed description on DDC I2C buffer description and OVS description), device power management, TMDS clock-detect feature, and TMDS input-port selection can be set. See through .
GPIO mode:When the I2C_SEL pin is set high, the device is in GPIO control mode. The port selection is controlled with source selectors, S1 and S2. The power-saving mode is controlled through theLPpin. In GPIO mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set, and the default DDC I2C buffer OVS setting (OVS3) is set. See and the for a detailed description of the DDC I2C buffer.
Following are some of the key features (advantages) that TMDS361B provides to the overall sink-side system (HDTV).
The TMDS361B is a three-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to three DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth. TMDS361B is not intended for source side applications such as external switch boxes.
The TMDS361B provides an adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps.
When any of the input ports are selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state.
The TMDS361B is designed to be controlled via a local I2C interface or GPIO interface based on the status of the I2C_SEL pin. The local I2C interface in TMDS361B is a slave-only I2C interface. (See the section.)
I2C Mode: When the I2C_SEL pin is set low, the device is in I2C mode. With local I2C, the interface port status can be read and the advanced configurations of the device such as TMDS output edge rate control, DDC I2C buffer output-voltage-select (OVS) settings (See the for detailed description on DDC I2C buffer description and OVS description), device power management, TMDS clock-detect feature, and TMDS input-port selection can be set. See through .
GPIO mode:When the I2C_SEL pin is set high, the device is in GPIO control mode. The port selection is controlled with source selectors, S1 and S2. The power-saving mode is controlled through theLPpin. In GPIO mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set, and the default DDC I2C buffer OVS setting (OVS3) is set. See and the for a detailed description of the DDC I2C buffer.
Following are some of the key features (advantages) that TMDS361B provides to the overall sink-side system (HDTV). |
TMDS4422.25-Gbps 4-to-2 DVI/HDMI1.3a mux | Integrated Circuits (ICs) | 1 | Active | The TMDS442, 4-to-2 port DVI/HDMI switch, allows up to 4 digital video interface (DVI) or high-definition multimedia interface (HDMI) ports to be switched to two independent display blocks. The essential requirement of picture-in-picture display from two digital audiovisual sources is having two individual DVI or HDMI receivers in a digital display system. TMDS442 supports two DVI or HDMI receivers to enable multiple-source selection (picture-in-picture), as well as supports acting as a 4-input 1-output video switch.
Each input or output port contains one 5-V power indicator (5V_PWR), one hot plug detector (HPD), a pair of I2C interface signals (SCL/SDA), and four TMDS channels supporting data rates up to 2.25 Gbps. The 5-V power indicator and the hot plug detector are pulled down with internal resistors, forcing a low state on these pins until receiving a valid high signal. The I2C interface is constructed by an I2C repeater circuit to isolate the capacitance form both ends of the buses. TMDS receivers integrate 50-termination resistors pulled up to VCC, which eliminates the need for external terminations. An 8-dB input equalization cooperates to each TMDS receiver inputs to optimize system performance through 5-meter or longer DVI or HDMI compliant cables.
A precision resistor is connected externally from the VSADJ pin to ground, for setting the differential output voltage to be compliant with the TMDS standard for all TMDS driver outputs. The PRE pin controls the TMDS output to be operated under either a standard TMDS mode or an AC de-emphasis mode. When PRE = high, a 3-dB AC de-emphasis TMDS output swing is selected to pre-condition the output signals to overcome signal impairments that may exist between the output of the TMDS442 and the HDMI receiver placed at a remote location.
Each sink output port can be configured with the SA, SB,OE, I2CEN, and PRE pins. SA1, SB1,OE1, I2CEN1, and PRE1 regulate the behaviour of sink port 1; SA2, SB2,OE2, I2CEN2, and PRE2 regulate the behaviour of sink port 2. These control signals are hard-wire controlled by GPIO interface, or through a local I2C interface. When GE = low, the configurations are done through a local I2C interface, LC_SCL, LC_SDA, LC_A0, and LC_A1 pins, and the 5V_EN can be programmed through the local I2C interface. It is default high after device powered on. When GE = high, the configurations are done through GPIO pins regardless the value of the 5V_EN in the internal I2C registers.
The two bit source selector pins, SA and SB, determine the source transferred to the sink port. The internal multiplexer interconnects the TMDS channels and I2C interface from the selected source port to the sink port. The HPD output of the selected source port follows the status of the HPD_SINK. Since two of the source ports will always be unconnected to any output, the I2C interfaces of unselected ports are isolated and the HPD outputs of an unselected port are pulled low.
The TMDS outputs of each of the sink ports are enabled based on theOEsignal and 5V_PWR signal (from the selected source port). WhenOEis low, for an output port, and the 5V_PWR signal from the selected source port is high, the TMDS output signals are enabled; otherwise they are disabled, and high impedance.
The I2C driver at sink side, SCL_SINK and SDA_SINK, are enabled by setting I2CEN high. When I2CEN is low, the I2C driver can not forward a low state to the I2C bus connected at the sink port. A hard wire output voltage select pin, OVS, allows adjustable output voltage level to SCL_SINK and SDA_SINK to optimise noise margins while interfacing to different HDMI receivers. The I2C driver of each source port, SCL and SDA, is controlled by its 5V_PWR signal. A valid 5-V signal appearing at the input of 5V_PWR enables the I2C driver of the source port.
The device is packaged in a 128-pin PowerPAD TQFP package and characterized for operation from 0°C to 70°C.
The TMDS442, 4-to-2 port DVI/HDMI switch, allows up to 4 digital video interface (DVI) or high-definition multimedia interface (HDMI) ports to be switched to two independent display blocks. The essential requirement of picture-in-picture display from two digital audiovisual sources is having two individual DVI or HDMI receivers in a digital display system. TMDS442 supports two DVI or HDMI receivers to enable multiple-source selection (picture-in-picture), as well as supports acting as a 4-input 1-output video switch.
Each input or output port contains one 5-V power indicator (5V_PWR), one hot plug detector (HPD), a pair of I2C interface signals (SCL/SDA), and four TMDS channels supporting data rates up to 2.25 Gbps. The 5-V power indicator and the hot plug detector are pulled down with internal resistors, forcing a low state on these pins until receiving a valid high signal. The I2C interface is constructed by an I2C repeater circuit to isolate the capacitance form both ends of the buses. TMDS receivers integrate 50-termination resistors pulled up to VCC, which eliminates the need for external terminations. An 8-dB input equalization cooperates to each TMDS receiver inputs to optimize system performance through 5-meter or longer DVI or HDMI compliant cables.
A precision resistor is connected externally from the VSADJ pin to ground, for setting the differential output voltage to be compliant with the TMDS standard for all TMDS driver outputs. The PRE pin controls the TMDS output to be operated under either a standard TMDS mode or an AC de-emphasis mode. When PRE = high, a 3-dB AC de-emphasis TMDS output swing is selected to pre-condition the output signals to overcome signal impairments that may exist between the output of the TMDS442 and the HDMI receiver placed at a remote location.
Each sink output port can be configured with the SA, SB,OE, I2CEN, and PRE pins. SA1, SB1,OE1, I2CEN1, and PRE1 regulate the behaviour of sink port 1; SA2, SB2,OE2, I2CEN2, and PRE2 regulate the behaviour of sink port 2. These control signals are hard-wire controlled by GPIO interface, or through a local I2C interface. When GE = low, the configurations are done through a local I2C interface, LC_SCL, LC_SDA, LC_A0, and LC_A1 pins, and the 5V_EN can be programmed through the local I2C interface. It is default high after device powered on. When GE = high, the configurations are done through GPIO pins regardless the value of the 5V_EN in the internal I2C registers.
The two bit source selector pins, SA and SB, determine the source transferred to the sink port. The internal multiplexer interconnects the TMDS channels and I2C interface from the selected source port to the sink port. The HPD output of the selected source port follows the status of the HPD_SINK. Since two of the source ports will always be unconnected to any output, the I2C interfaces of unselected ports are isolated and the HPD outputs of an unselected port are pulled low.
The TMDS outputs of each of the sink ports are enabled based on theOEsignal and 5V_PWR signal (from the selected source port). WhenOEis low, for an output port, and the 5V_PWR signal from the selected source port is high, the TMDS output signals are enabled; otherwise they are disabled, and high impedance.
The I2C driver at sink side, SCL_SINK and SDA_SINK, are enabled by setting I2CEN high. When I2CEN is low, the I2C driver can not forward a low state to the I2C bus connected at the sink port. A hard wire output voltage select pin, OVS, allows adjustable output voltage level to SCL_SINK and SDA_SINK to optimise noise margins while interfacing to different HDMI receivers. The I2C driver of each source port, SCL and SDA, is controlled by its 5V_PWR signal. A valid 5-V signal appearing at the input of 5V_PWR enables the I2C driver of the source port.
The device is packaged in a 128-pin PowerPAD TQFP package and characterized for operation from 0°C to 70°C. |
TMDS4613-Gbps 4-to-1 HDMI/DVI mux with adaptive equalization | Interface | 2 | NRND | The TMDS461 is a 4-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to four DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth.
The TMDS461 provides an analog adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps (see Figure 19).
When any input port is selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state.
The TMDS461 is designed to be controlled via a local I2C interface or GPIO interface based on the status of the I2C_SEL pin. The local I2C interface in TMDS461 is a slave-only I2C interface. (See the I2C INTERFACE NOTES section.)
I2C Mode: When the I2C_SEL pin is set high, the device is in I2C mode. Refer to Table 7 to Table 13 for I2C register description. With local I2C, the interface port status can be read and the advanced configurations of the device such as TMDS output edge rate control, DDC I2C buffer output-voltage-select (OVS) settings (See the DDC 12C FUNCTION DESCRIPTION for detailed description on DDC I2C buffer description and OVS description), device power management, TMDS clock-detect feature,Automatic Port Selectionand TMDS input-port selection can be set. In I2C mode when any system level change such as change in 5V_PWR on the source side, a change in the selected port, or a change in the selected port's valid clock detect is detected, TMDS461 can issue an Interrupt Request via IRQ pin (refer IRQ SECTION). A micro-controller connected to TMDS461 can read I2C register address 0X01, (See Table 7) to obtain the current status of 5V_PWR, the selected port, and clock-detect status. Once the micro-controller has read I2C register 0x01, the IRQ pin returns to low.
GPIO mode:When the I2C_SEL pin is set low, the device is in GPIO control mode. The port selection is controlled with source selectors, S1 and S2. The power-saving mode is controlled through theLPpin. In GPIO mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set. The DDC I2C buffer OVS setting can be changed through OVS GPIO pin, see Table 2. In GPIO mode, IRQ pin reflects the status of the selected port's clock detect. If a valid clock is detected by the clock detect circuit, IRQ goes high. If no valid clock is detected, IRQ is driven low.
Following are some of the key features (advantages) that TMDS461 provides to the overall sink-side system (HDTV).
The TMDS461 is a 4-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to four DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth.
The TMDS461 provides an analog adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps (see Figure 19).
When any input port is selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state.
The TMDS461 is designed to be controlled via a local I2C interface or GPIO interface based on the status of the I2C_SEL pin. The local I2C interface in TMDS461 is a slave-only I2C interface. (See the I2C INTERFACE NOTES section.)
I2C Mode: When the I2C_SEL pin is set high, the device is in I2C mode. Refer to Table 7 to Table 13 for I2C register description. With local I2C, the interface port status can be read and the advanced configurations of the device such as TMDS output edge rate control, DDC I2C buffer output-voltage-select (OVS) settings (See the DDC 12C FUNCTION DESCRIPTION for detailed description on DDC I2C buffer description and OVS description), device power management, TMDS clock-detect feature,Automatic Port Selectionand TMDS input-port selection can be set. In I2C mode when any system level change such as change in 5V_PWR on the source side, a change in the selected port, or a change in the selected port's valid clock detect is detected, TMDS461 can issue an Interrupt Request via IRQ pin (refer IRQ SECTION). A micro-controller connected to TMDS461 can read I2C register address 0X01, (See Table 7) to obtain the current status of 5V_PWR, the selected port, and clock-detect status. Once the micro-controller has read I2C register 0x01, the IRQ pin returns to low.
GPIO mode:When the I2C_SEL pin is set low, the device is in GPIO control mode. The port selection is controlled with source selectors, S1 and S2. The power-saving mode is controlled through theLPpin. In GPIO mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set. The DDC I2C buffer OVS setting can be changed through OVS GPIO pin, see Table 2. In GPIO mode, IRQ pin reflects the status of the selected port's clock detect. If a valid clock is detected by the clock detect circuit, IRQ goes high. If no valid clock is detected, IRQ is driven low.
Following are some of the key features (advantages) that TMDS461 provides to the overall sink-side system (HDTV). |
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