TMDS461 Series

The TMDS461 is a 4-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to four DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth. The TMDS461 provides an analog adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps (see Figure 19). When any input port is selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state. The TMDS461 is designed to be controlled via a local I2C interface or GPIO interface based on the status of the I2C_SEL pin. The local I2C interface in TMDS461 is a slave-only I2C interface. (See the I2C INTERFACE NOTES section.) I2C Mode: When the I2C_SEL pin is set high, the device is in I2C mode. Refer to Table 7 to Table 13 for I2C register description. With local I2C, the interface port status can be read and the advanced configurations of the device such as TMDS output edge rate control, DDC I2C buffer output-voltage-select (OVS) settings (See the DDC 12C FUNCTION DESCRIPTION for detailed description on DDC I2C buffer description and OVS description), device power management, TMDS clock-detect feature,Automatic Port Selectionand TMDS input-port selection can be set. In I2C mode when any system level change such as change in 5V_PWR on the source side, a change in the selected port, or a change in the selected port's valid clock detect is detected, TMDS461 can issue an Interrupt Request via IRQ pin (refer IRQ SECTION). A micro-controller connected to TMDS461 can read I2C register address 0X01, (See Table 7) to obtain the current status of 5V_PWR, the selected port, and clock-detect status. Once the micro-controller has read I2C register 0x01, the IRQ pin returns to low. GPIO mode:When the I2C_SEL pin is set low, the device is in GPIO control mode. The port selection is controlled with source selectors, S1 and S2. The power-saving mode is controlled through theLPpin. In GPIO mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set. The DDC I2C buffer OVS setting can be changed through OVS GPIO pin, see Table 2. In GPIO mode, IRQ pin reflects the status of the selected port's clock detect. If a valid clock is detected by the clock detect circuit, IRQ goes high. If no valid clock is detected, IRQ is driven low. Following are some of the key features (advantages) that TMDS461 provides to the overall sink-side system (HDTV). The TMDS461 is a 4-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to four DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth. The TMDS461 provides an analog adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps (see Figure 19). When any input port is selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state. The TMDS461 is designed to be controlled via a local I2C interface or GPIO interface based on the status of the I2C_SEL pin. The local I2C interface in TMDS461 is a slave-only I2C interface. (See the I2C INTERFACE NOTES section.) I2C Mode: When the I2C_SEL pin is set high, the device is in I2C mode. Refer to Table 7 to Table 13 for I2C register description. With local I2C, the interface port status can be read and the advanced configurations of the device such as TMDS output edge rate control, DDC I2C buffer output-voltage-select (OVS) settings (See the DDC 12C FUNCTION DESCRIPTION for detailed description on DDC I2C buffer description and OVS description), device power management, TMDS clock-detect feature,Automatic Port Selectionand TMDS input-port selection can be set. In I2C mode when any system level change such as change in 5V_PWR on the source side, a change in the selected port, or a change in the selected port's valid clock detect is detected, TMDS461 can issue an Interrupt Request via IRQ pin (refer IRQ SECTION). A micro-controller connected to TMDS461 can read I2C register address 0X01, (See Table 7) to obtain the current status of 5V_PWR, the selected port, and clock-detect status. Once the micro-controller has read I2C register 0x01, the IRQ pin returns to low. GPIO mode:When the I2C_SEL pin is set low, the device is in GPIO control mode. The port selection is controlled with source selectors, S1 and S2. The power-saving mode is controlled through theLPpin. In GPIO mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set. The DDC I2C buffer OVS setting can be changed through OVS GPIO pin, see Table 2. In GPIO mode, IRQ pin reflects the status of the selected port's clock detect. If a valid clock is detected by the clock detect circuit, IRQ goes high. If no valid clock is detected, IRQ is driven low. Following are some of the key features (advantages) that TMDS461 provides to the overall sink-side system (HDTV).