Texas Instruments

The SN75DP129 is a Dual-Mode DisplayPort input to Transition-Minimized Differential Signaling (TMDS) output. The TMDS output has a built-in level translator, compliant with Digital Visual Interface 1.0 (DVI) and High Definition Multimedia Interface 1.3 (HDMI) standards. The SN75DP129 is specified up to a maximum data rate of 2.5 Gbps, supporting resolutions greater then 1920 x 1200 or HDTV 12-bit color depth at 1080p (progressive scan). An integrated Active I2C buffer isolates the capacitive loading of the source system from that of the sink and interconnecting cable. This isolation improves overall signal integrity of the system and provides greater design margin within the source system for DVI / HDMI compliance testing. A logic block was designed into the SN75DP129 to assist with TMDS connector identification. Through the use of the I2C_EN pin, this logic block can be enabled to indicate the translated port is an HDMI port; therefore legally supporting HDMI content. The SN75DP129 is a Dual-Mode DisplayPort input to Transition-Minimized Differential Signaling (TMDS) output. The TMDS output has a built-in level translator, compliant with Digital Visual Interface 1.0 (DVI) and High Definition Multimedia Interface 1.3 (HDMI) standards. The SN75DP129 is specified up to a maximum data rate of 2.5 Gbps, supporting resolutions greater then 1920 x 1200 or HDTV 12-bit color depth at 1080p (progressive scan). An integrated Active I2C buffer isolates the capacitive loading of the source system from that of the sink and interconnecting cable. This isolation improves overall signal integrity of the system and provides greater design margin within the source system for DVI / HDMI compliance testing. A logic block was designed into the SN75DP129 to assist with TMDS connector identification. Through the use of the I2C_EN pin, this logic block can be enabled to indicate the translated port is an HDMI port; therefore legally supporting HDMI content.

The SN75DP130 device is a single channel DisplayPort™ (DP) re-driver that regenerates the DP high-speed digital link. The device complies with the VESA DisplayPort Standard Version 1.2, and supports a 4-lane Main Link interface signaling up to HBR2 rates at 5.4 Gbps per lane. This device also supports DP++ Dual-Mode, offering TMDS signaling for DVI and full HDMI Version 1.4a support. The device compensates for PCB-related frequency loss and switching-related loss to provide the optimum DP electrical performance from source to sink. The Main Link signal inputs feature configurable equalizers with selectable boost settings. At the Main Link output, four primary levels of differential output voltage swing (VOD) and four primary levels of pre-emphasis are available. A secondary level of boost adjustment, programmed through I2C, for fine-tuning the Main Link output. The device can monitor the AUX channel and automatically adjust the output signaling levels and input equalizers in response to Link Training commands. Additionally, the SN75DP130 output signal conditioning and EQ parameters are fully programmable through the I2C interface. The SN75DP130 is optimized for mobile applications, and contains activity detection circuitry on the Main Link input that transitions to a low-power Output Disable mode in the absence of a valid input signal. Other low-power modes are supported, including a standby mode with typical dissipation of approximately 2 mW when no video sink (for example, monitor) is connected. The device is characterized for an extended operational temperature range from 0°C to 85°C. The SN75DP130 offers separate AUX and DDC source interfaces that connect to one AUX sink channel. This minimizes component count when implemented with a graphics processor (GPU) comprising separate DDC and AUX interfaces. For GPUs with combined DDC/AUX, the device can operate as a FET switch to short-circuit the AUX channel AC coupling caps while connected to a TMDS sink device. Other sideband circuits such as Hot Plug Detect (HPD) are optimized to reduce external components, providing a seamless connection to Intel, AMD, and NVIDIA graphics processors. The SN75DP130 device is a single channel DisplayPort™ (DP) re-driver that regenerates the DP high-speed digital link. The device complies with the VESA DisplayPort Standard Version 1.2, and supports a 4-lane Main Link interface signaling up to HBR2 rates at 5.4 Gbps per lane. This device also supports DP++ Dual-Mode, offering TMDS signaling for DVI and full HDMI Version 1.4a support. The device compensates for PCB-related frequency loss and switching-related loss to provide the optimum DP electrical performance from source to sink. The Main Link signal inputs feature configurable equalizers with selectable boost settings. At the Main Link output, four primary levels of differential output voltage swing (VOD) and four primary levels of pre-emphasis are available. A secondary level of boost adjustment, programmed through I2C, for fine-tuning the Main Link output. The device can monitor the AUX channel and automatically adjust the output signaling levels and input equalizers in response to Link Training commands. Additionally, the SN75DP130 output signal conditioning and EQ parameters are fully programmable through the I2C interface. The SN75DP130 is optimized for mobile applications, and contains activity detection circuitry on the Main Link input that transitions to a low-power Output Disable mode in the absence of a valid input signal. Other low-power modes are supported, including a standby mode with typical dissipation of approximately 2 mW when no video sink (for example, monitor) is connected. The device is characterized for an extended operational temperature range from 0°C to 85°C. The SN75DP130 offers separate AUX and DDC source interfaces that connect to one AUX sink channel. This minimizes component count when implemented with a graphics processor (GPU) comprising separate DDC and AUX interfaces. For GPUs with combined DDC/AUX, the device can operate as a FET switch to short-circuit the AUX channel AC coupling caps while connected to a TMDS sink device. Other sideband circuits such as Hot Plug Detect (HPD) are optimized to reduce external components, providing a seamless connection to Intel, AMD, and NVIDIA graphics processors.

The SN75DP139 is a dual-mode DisplayPort input to Transition-Minimized Differential Signaling (TMDS) output. The TMDS output has a built-in level-shifting re-driver supporting Digital Video Interface (DVI) 1.0 and High Definition Multimedia Interface (HDMI) 1.4b standards. The SN75DP139 is specified up to a maximum data rate of 3.4 Gbps, supporting resolutions greater then 1920 × 1200 or HDTV 12-bit color depth at 1080p (progressive scan). The SN75DP139 is compliant with the HDMI 1.4b specifications and supports optional protocol enhancements such as 3D graphics at resolutions demanding a pixel rate up to 340 MHz. The SN75DP139 is a dual-mode DisplayPort input to Transition-Minimized Differential Signaling (TMDS) output. The TMDS output has a built-in level-shifting re-driver supporting Digital Video Interface (DVI) 1.0 and High Definition Multimedia Interface (HDMI) 1.4b standards. The SN75DP139 is specified up to a maximum data rate of 3.4 Gbps, supporting resolutions greater then 1920 × 1200 or HDTV 12-bit color depth at 1080p (progressive scan). The SN75DP139 is compliant with the HDMI 1.4b specifications and supports optional protocol enhancements such as 3D graphics at resolutions demanding a pixel rate up to 340 MHz.

The SNx5DP149 device is a dual mode DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b output signals. The SNx5DP149 device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link. The SNx5DP149 device supports data rate up to 3.4-Gbps per data lane to support Ultra HD (4K × 2K / 30-Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 × 1080 / 60-Hz). The SNx5DP149 device can automatically configure itself as a re-driver at data rates <1 Gbps, or as a retimer at more than this data rate. This feature can be turned off through I2C programming. For signal integrity, the SNx5DP149 device implements several features. The SNx5DP149 receiver supports both adaptive and fixed equalization to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces or cables. When working as a retimer, the embedded clock data recovery (CDR) cleans up the input high frequency and random jitter from video source. The transmitter provides several features for passing compliance and reducing system-level design issues like de-emphasis, which compensates for the attenuation when driving long cables or high-loss board traces. The SNx5DP149 device also includes TMDS output amplitude adjust using an external resistor on the Vsadj pin, source termination selection, and output slew rate control. Device operation and configuration can be programmed by pin strapping or I2C. The SNx5DP149 device implements several methods for power management and active power reduction. The SNx5DP149 receiver comes in a 40-pin RSB supporting space-constrained applications. The SN65DP149 device is characterized for an industrial operational temperature range from –40°C to 85°C. The SN75DP149 device is characterized for an extended commercial operational temperature range from 0°C to 85°C. The SNx5DP149 device is a dual mode DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b output signals. The SNx5DP149 device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link. The SNx5DP149 device supports data rate up to 3.4-Gbps per data lane to support Ultra HD (4K × 2K / 30-Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 × 1080 / 60-Hz). The SNx5DP149 device can automatically configure itself as a re-driver at data rates <1 Gbps, or as a retimer at more than this data rate. This feature can be turned off through I2C programming. For signal integrity, the SNx5DP149 device implements several features. The SNx5DP149 receiver supports both adaptive and fixed equalization to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces or cables. When working as a retimer, the embedded clock data recovery (CDR) cleans up the input high frequency and random jitter from video source. The transmitter provides several features for passing compliance and reducing system-level design issues like de-emphasis, which compensates for the attenuation when driving long cables or high-loss board traces. The SNx5DP149 device also includes TMDS output amplitude adjust using an external resistor on the Vsadj pin, source termination selection, and output slew rate control. Device operation and configuration can be programmed by pin strapping or I2C. The SNx5DP149 device implements several methods for power management and active power reduction. The SNx5DP149 receiver comes in a 40-pin RSB supporting space-constrained applications. The SN65DP149 device is characterized for an industrial operational temperature range from –40°C to 85°C. The SN75DP149 device is characterized for an extended commercial operational temperature range from 0°C to 85°C.

The SNx5DP159 device is a dual mode[1] DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b and 2.0b output signals. The SNx5DP159 device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link or AUX channel. The SNx5DP159 device supports data rate up to 6-Gbps per data lane to support Ultra HD (4K × 2K / 60-Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 × 1080 / 60-Hz). The SNx5DP159 device can automatically configure itself as a re-driver at data rates <1 Gbps, or as a retimer at more than this data rate. This feature can be turned off through I2C[4] programming. For signal integrity, the SNx5DP159 device implements several features. The SNx5DP159 receiver supports both adaptive and fixed equalization to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces or cables. When working as a retimer, the embedded clock data recovery (CDR) cleans up the input high frequency and random jitter from video source. The transmitter provides several features for passing compliance and reducing system-level design issues like de-emphasis, which compensates for the attenuation when driving long cables or high-loss board traces. The SNx5DP159 device also includes TMDS output amplitude adjust using an external resistor on the Vsadj pin, source termination selection, and output slew rate control. Device operation and configuration can be programmed by pin strapping or I2C[4]. The SNx5DP159 device implements several methods for power management and active power reduction. The SNx5DP159 receiver uses several methods to determine whether the application supports HDMI1.4b[2] or HDMI2.0[3] data rates. The SNx5DP159 receiver comes in two packages: a 40-pin RSB supporting space-constrained applications and a 48-pin RGZ version supporting the full feature set for DisplayPort dual-mode standard version 1.1 in applications such as dongles. The SN65DP159 device is characterized for an industrial operational temperature range from –40°C to 85°C. The SN75DP159 device is characterized for an extended commercial operational temperature range from 0°C to 85°C. The SNx5DP159 device is a dual mode[1] DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b and 2.0b output signals. The SNx5DP159 device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link or AUX channel. The SNx5DP159 device supports data rate up to 6-Gbps per data lane to support Ultra HD (4K × 2K / 60-Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 × 1080 / 60-Hz). The SNx5DP159 device can automatically configure itself as a re-driver at data rates <1 Gbps, or as a retimer at more than this data rate. This feature can be turned off through I2C[4] programming. For signal integrity, the SNx5DP159 device implements several features. The SNx5DP159 receiver supports both adaptive and fixed equalization to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces or cables. When working as a retimer, the embedded clock data recovery (CDR) cleans up the input high frequency and random jitter from video source. The transmitter provides several features for passing compliance and reducing system-level design issues like de-emphasis, which compensates for the attenuation when driving long cables or high-loss board traces. The SNx5DP159 device also includes TMDS output amplitude adjust using an external resistor on the Vsadj pin, source termination selection, and output slew rate control. Device operation and configuration can be programmed by pin strapping or I2C[4]. The SNx5DP159 device implements several methods for power management and active power reduction. The SNx5DP159 receiver uses several methods to determine whether the application supports HDMI1.4b[2] or HDMI2.0[3] data rates. The SNx5DP159 receiver comes in two packages: a 40-pin RSB supporting space-constrained applications and a 48-pin RGZ version supporting the full feature set for DisplayPort dual-mode standard version 1.1 in applications such as dongles. The SN65DP159 device is characterized for an industrial operational temperature range from –40°C to 85°C. The SN75DP159 device is characterized for an extended commercial operational temperature range from 0°C to 85°C.

The DPHY440 is a 1-lane to 4-lane and clock MIPI DPHY retimer that regenerates the DPHY signaling. The device complies with MIPI DPHY 1.1 standard and can be used in either a MIPI CSI-2 or MIPI DSI application at datarates of up to 1.5Gbps. The device compensates for PCB, connector, and cable related frequency loss and switching related loss to provide the optimum electrical performance from a CSI-2/DSI source to sink. The DPHY440 DPHY inputs feature configurable equalizers. The output pins automatically compensate for uneven skew between clock and data lanes received on the inputs ports of the device. The DPHY440 output voltage swing and edge rate can be adjusted by changing the state of the VSADJ_CFG0 pin and ERC pin, respectively. The DPHY440 is optimized for mobile applications, and contains activity detection circuitry on the DPHY Link interface that can transition into a lower power mode when in ULPS and LP states. The SN65DPHY440SS is characterized for an industrial temperature range from –40°C to 85°C while SN75DPHY440SS is characterized for commercial temperature range from 0°C to 70°C. The DPHY440 is a 1-lane to 4-lane and clock MIPI DPHY retimer that regenerates the DPHY signaling. The device complies with MIPI DPHY 1.1 standard and can be used in either a MIPI CSI-2 or MIPI DSI application at datarates of up to 1.5Gbps. The device compensates for PCB, connector, and cable related frequency loss and switching related loss to provide the optimum electrical performance from a CSI-2/DSI source to sink. The DPHY440 DPHY inputs feature configurable equalizers. The output pins automatically compensate for uneven skew between clock and data lanes received on the inputs ports of the device. The DPHY440 output voltage swing and edge rate can be adjusted by changing the state of the VSADJ_CFG0 pin and ERC pin, respectively. The DPHY440 is optimized for mobile applications, and contains activity detection circuitry on the DPHY Link interface that can transition into a lower power mode when in ULPS and LP states. The SN65DPHY440SS is characterized for an industrial temperature range from –40°C to 85°C while SN75DPHY440SS is characterized for commercial temperature range from 0°C to 70°C.

The SN65HVD05, SN75HVD05, SN65HVD06, SN75HVD06, SN65HVD07, and SN75HVD07 combine a 3-state differential line driver and differential line receiver. They are designed for balanced data transmission and interoperate with ANSI TIA/EIA-485-A and ISO 8482E standard-compliant devices. The driver is designed to provide a differential output voltage greater than that required by these standards for increased noise margin. The drivers and receivers have active-high and active-low enables respectively, which can be externally connected together to function as direction control. The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or not powered. These devices feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications. The SN65HVD05, SN75HVD05, SN65HVD06, SN75HVD06, SN65HVD07, and SN75HVD07 combine a 3-state differential line driver and differential line receiver. They are designed for balanced data transmission and interoperate with ANSI TIA/EIA-485-A and ISO 8482E standard-compliant devices. The driver is designed to provide a differential output voltage greater than that required by these standards for increased noise margin. The drivers and receivers have active-high and active-low enables respectively, which can be externally connected together to function as direction control. The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or not powered. These devices feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications.

The SN65HVD05, SN75HVD05, SN65HVD06, SN75HVD06, SN65HVD07, and SN75HVD07 combine a 3-state differential line driver and differential line receiver. They are designed for balanced data transmission and interoperate with ANSI TIA/EIA-485-A and ISO 8482E standard-compliant devices. The driver is designed to provide a differential output voltage greater than that required by these standards for increased noise margin. The drivers and receivers have active-high and active-low enables respectively, which can be externally connected together to function as direction control. The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or not powered. These devices feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications. The SN65HVD05, SN75HVD05, SN65HVD06, SN75HVD06, SN65HVD07, and SN75HVD07 combine a 3-state differential line driver and differential line receiver. They are designed for balanced data transmission and interoperate with ANSI TIA/EIA-485-A and ISO 8482E standard-compliant devices. The driver is designed to provide a differential output voltage greater than that required by these standards for increased noise margin. The drivers and receivers have active-high and active-low enables respectively, which can be externally connected together to function as direction control. The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or not powered. These devices feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications.

The SN65HVD05, SN75HVD05, SN65HVD06, SN75HVD06, SN65HVD07, and SN75HVD07 combine a 3-state differential line driver and differential line receiver. They are designed for balanced data transmission and interoperate with ANSI TIA/EIA-485-A and ISO 8482E standard-compliant devices. The driver is designed to provide a differential output voltage greater than that required by these standards for increased noise margin. The drivers and receivers have active-high and active-low enables respectively, which can be externally connected together to function as direction control. The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or not powered. These devices feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications. The SN65HVD05, SN75HVD05, SN65HVD06, SN75HVD06, SN65HVD07, and SN75HVD07 combine a 3-state differential line driver and differential line receiver. They are designed for balanced data transmission and interoperate with ANSI TIA/EIA-485-A and ISO 8482E standard-compliant devices. The driver is designed to provide a differential output voltage greater than that required by these standards for increased noise margin. The drivers and receivers have active-high and active-low enables respectively, which can be externally connected together to function as direction control. The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or not powered. These devices feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications.